A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

This paper has presented a comprehensive overview of on-chip antennas, which remain the last bottleneck for achieving true SoC RF solutions. CMOS remains the mainstream IC technology choice but is not well suited for on-chip antennas, requiring the use of innovative design techniques to overcome its shortcomings. Codesign of circuits and antennas provide leverage to the designer to achieve optimum performance. The layout of on-chip antennas is dictated by foundry specific rules whereas characterization of on-chip antennas requires special text fixtures. For future highly integrated SoC solutions, foundries will have to provide special layers for efficient on-chip antenna implementations, as they currently do for on-chip inductors. In many of the emerging applications such as THz communication, implantable systems and energy harvesting, on-chip antennas have shown immense potential and are likely to play a major role in shaping up future communication systems.

The last barrier: on-chip antennas

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.

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A Class-F CMOS Oscillator

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

We are approaching an age of IoT, in which sensors and controllers in all types of devices, including smart phones and PCs, are connected together. The strongest candidate fora wireless interface is the Bluetooth Low Energy® (BLE) standard because it is already widely used in smart phones. Many markets, especially for wearable devices like smart watches, demand BLE devices with a small module area and low current consumption. In previous research, solutions to the requirements for BLE have been widely discussed such as using the sliding IF (SIF) architecture in the RX [1,2] and a Class-D amplifier [2] with HD2 calibration [4] in the TX to achieve lower current consumption. The SIF architecture, however, involves RF image blocking violation without exception rule or the use of additional off-chip filters. In the TX, meanwhile, the calibration incurs a weakness in terms of the offset issue. Moreover, there is no approach to achieve "zero" external components for the RF port. In this paper, a BLE transceiver, with a reconfigurable filter, embedded into an on-chip matching network without any external components, is presented.

13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network

A 5 mm2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.

A 5 mm $^{2}$ 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

SDRs come of age ([1,2]) and transcend beyond just acquiring the reconfigura-bility to replace any standard radio: they develop toward systems where a simplified antenna interface can be used, with most dedicated filtering removed. This requires a receiver accommodating much higher linearity and resilience against out-of-band interference than a standard radio, still achieving competitive sensitivity (especially in the absence of interference). Mixer-first front-ends with excellent linearity have been reported [3]. However, their NF (including 1/f in absence of the LNA gain) is not competitive, and they may suffer from large LO feedthrough to the antenna (LOFT). Moreover they lack receiver functionality such as gain and filtering, which cannot be simply added without compromising linearity. A receiver with mixer-at-the-antenna-based bandpass filter [4] similarly may suffer from LOFT and increased N F. This work presents a full software-defined receiver with 3dB NF that tolerates 0dBm blockers with acceptable blocker NF at maximum gain. It achieves +10dBm out-of-band (OB) IIP3 and >+70dBm IIP2. Such a receiver is to operate using no other than harmonic-rejection filtering.

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio (SDR) in deeply scaled CMOS. This is enhanced with the advent of LTE, a standard that is inherently so flexible that an SDR is its most economical implementation. This work presents an answer to that need with the development of a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.

Tomohiro Sano

Papers

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network

A 5 mm $^{2}$ 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

A 5mm 2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver