Proceedings ArticleDOI
A 5mm 2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver
Mark Ingels,Vito Giannini,Jonathan Borremans,Gunjan Mandal,Bjorn Debaillie,Peter Van Wesemael,Tomohiro Sano,Takaya Yamamoto,Dries Hauspie,Joris Van Driessche,Jan Craninckx +10 more
- pp 458-459
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TLDR
The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio in deeply scaled CMOS, resulting in the need for a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.Abstract:
The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio (SDR) in deeply scaled CMOS. This is enhanced with the advent of LTE, a standard that is inherently so flexible that an SDR is its most economical implementation. This work presents an answer to that need with the development of a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.read more
Citations
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Journal ArticleDOI
The last barrier: on-chip antennas
Hammad M. Cheema,Atif Shamim +1 more
TL;DR: In many of the emerging applications such as THz communication, implantable systems and energy harvesting, on-chip antennas have shown immense potential and are likely to play a major role in shaping up future communication systems.
Journal ArticleDOI
A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers
Jonathan Borremans,G. Mandal,Vito Giannini,Bjorn Debaillie,Mark Ingels,Tomohiro Sano,Bob Verbruggen,Jan Craninckx +7 more
TL;DR: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna thanks to a 2.5 V linear LNA and mixer-based RF blocker filter.
Proceedings ArticleDOI
A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode
Zdravko Boos,Andreas Menkhoff,Franz Kuttner,Markus Schimper,Jose Pedro Moreira,Hans Geltinger,Timo Gossmann,Peter Pfann,Alexander Belitzer,Thomas Bauernfeind +9 more
TL;DR: It is necessary to develop a transmitter architecture that enables use of a multimode, multiband power amplifier, a key prerequisite to substantially reduce the number of external components, pins count, and PCB area, while at the same time significantly lowering power consumption.
Proceedings ArticleDOI
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers
Jonathan Borremans,Gunjan Mandal,Vito Giannini,Tomohiro Sano,Mark Ingels,Bob Verbruggen,Jan Craninckx +6 more
TL;DR: This work presents a full software-defined receiver with 3dB NF that tolerates 0dBm blockers with acceptable blocker NF at maximum gain and achieves +10dBm out-of-band IIP3 and >+70dBm IIP2.
Proceedings ArticleDOI
A multiband LTE SAW-less modulator with −160dBc/Hz RX-band noise in 40nm LP CMOS
TL;DR: In FDD cellular standards, the transmitter's out of-band noise leaks into the receive band due to the finite duplexer TX to RX isolation if this noise is not low enough, a SAW filter is needed before the Power Amplifier to preserve the RX sensitivity.
References
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Journal ArticleDOI
An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS
R. Bagheri,Ahmad Mirzaei,S. Chehrazi,M.E. Heidari,Minjae Lee,Mohyee Mikhemar,Wai Tang,Asad A. Abidi +7 more
TL;DR: In this paper, a software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters.
Proceedings ArticleDOI
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
TL;DR: SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range, but when the comparator determines in first instance the overall performance, comparator thermal noise can limit the maximum achievable resolution.
Journal ArticleDOI
Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS
TL;DR: It is demonstrated that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).
Journal ArticleDOI
A Multimode Transmitter in 0.13 $\mu\hbox{m}$ CMOS Using Direct-Digital RF Modulator
TL;DR: A system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block is presented.
Proceedings ArticleDOI
Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset
C. Jones,Bernard Mark Tenbroek,P. Fowers,C. Beghein,Jonathan Richard Strange,F. Beffa,D. Nalbantis +6 more
TL;DR: A direct-conversion multi-band TX for 1710 to 2025MHz is implemented in a 0.18mum CMOS process with post-passivation inductors and an on-chip balun and noise enable the PA to be driven directly with no SAW filter.