A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

3D semiconductor device and structure

This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Using imaging techniques to determine if stacked wafers are in proper alignment. An infrared radiation source and an infrared camera are positioned on opposing sides of a stacked wafer. The infrared radiation source emits infrared radiation that penetrates and passes through the stacked wafer. The infrared radiation is then captured by the infrared camera. Fiducial marks that were previously patterned on each wafer of the stack are exposed in an image produced by the captured infrared radiation. The degree of alignment of the wafers can be measured using the fiducial marks exposed in the image.

Metrology system and method for stacked wafer alignment

A novel optical probing technique to measure voltage waveforms from flip-chip packaged CMOS integrated circuits (IC) is described. This IR laser based technique allows signal waveform acquisition and high frequency timing measurements directly from active P-N junctions through the silicon backside substrate on ICs mounted in flip-chip stand-alone or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug and failure analysis (FA) throughput time (TPT) as compared to backside electron-beam (e-beam) probing because of the elimination of backside trenching and probe hole generation operations.

Laser voltage probe (LVP): a novel optical probing technology for flip-chip packaged microprocessors

Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions. In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included. In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.

MOSFET-based power supply clamps for electrostatic discharge protection of integrated circuits

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Travis Eiles

Papers

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Metrology system and method for stacked wafer alignment

Laser voltage probe (LVP): a novel optical probing technology for flip-chip packaged microprocessors

MOSFET-based power supply clamps for electrostatic discharge protection of integrated circuits

Isolation structure configurations for modifying stresses in semiconductor devices