W
W.J. Taylor
Researcher at Freescale Semiconductor
Publications - 21
Citations - 287
W.J. Taylor is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Metal gate & High-κ dielectric. The author has an hindex of 9, co-authored 21 publications receiving 282 citations.
Papers
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Proceedings ArticleDOI
Challenges for the integration of metal gate electrodes
James K. Schaeffer,C. Capasso,L. R. C. Fonseca,S. Samavedam,David C. Gilmer,Yong Liang,S. Kalpat,B. Adetutu,Hsing-Huang Tseng,Y. Shiho,Alexander A. Demkov,Rama I. Hegde,W.J. Taylor,Rich Gregory,J. Jiang,E. Luckowski,M. Raymond,K. Moore,Dina H. Triyoso,D. Roan,B. E. White,Philip J. Tobin +21 more
TL;DR: In this article, the integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed.
Proceedings ArticleDOI
Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stack
H.-H. Tseng,C. Capasso,James K. Schaeffer,E.A. Hebert,Philip J. Tobin,David C. Gilmer,Dina H. Triyoso,M. Ramon,S. Kalpat,E. Luckowski,W.J. Taylor,Y. Jeon,Olubunmi O. Adetutu,Rama I. Hegde,R. Noble,M. Jahanbani,C. El Chemali,B. E. White +17 more
TL;DR: In this article, a novel stress relieved preoxide (SRPO) followed by ALD of HfO/sub 2/ reduces the local charge density near the gate edge and short channel threshold voltage instability.
Proceedings ArticleDOI
Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]
Srikanth B. Samavedam,L.B. La,Philip J. Tobin,Bruce E. White,Christopher C. Hobbs,L. R. C. Fonseca,Alexander A. Demkov,J. Schaeffer,E. Luckowski,Arturo M. Martinez,Mark V. Raymond,D. Triyoso,D. Roan,V. Dhandapani,R. Garcia,S.G.H. Anderson,K. Moore,H.-H. Tseng,C. Capasso,O. Adetutu,David Gilmer,W.J. Taylor,Rama I. Hegde,J. M. Grant +23 more
TL;DR: In this article, the impact of small and systematic changes at the metal/dielectric interface on metal work-function was examined and the Fermi level pinning of TaN, TaSiN and TiN gates was reported.
Patent
Dual gate oxide device integration
TL;DR: In this paper, a method of forming devices including forming a first region and a second region in a semiconductor substrate is provided, which includes forming a semiconductive material over the first region, wherein the semiconductorive material has a different electrical property than the first substrate.
Journal ArticleDOI
Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics
David C. Gilmer,James K. Schaeffer,W.J. Taylor,C. Capasso,K. Junker,J. Hildreth,D. Tekleab,Brian A. Winstead,S. Samavedam +8 more
TL;DR: In this article, the tradeoffs in using different combinations of thin-strained Si 1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology were explored.