W. Shao

TL;DR: In this article, the effect of reservoir at the copper via region on electromigration performance was studied using via-fed two-layer test structures with various extension lengths above the via, consistent with the mechanism of vacancy movement along the Cu/Si3N4 interface.

TL;DR: In this paper, package level stress migration test of Cu dual-damascene interconnects in via-line structures was performed, and the effects of stressing temperature and dielectric materials on SIV behavior were investigated.

TL;DR: In this paper, the influence of Ml (lower level Cu) line width on stress-induced voiding behavior of copper dual damascene interconnects was investigated by stress migration test at 200 °C and finite element analysis (FEA).

TL;DR: In this paper, the effect of modifying the Cu/dielectric cap interface on electromigration EM in dual-damascene interconnect structures is presented, where the Cu surface was treated with reducing NH3,H 2 and reactive SiH4 gases immediately after chemical mechanical polishing, but prior to SiNx dielectric capping.

TL;DR: In this paper, the impact of electron wind force on void evolution, agglomeration at the Cu/cap/liner edges, and interface diffusion was investigated based on morphological examinations.