Hans-Juergen Engelmann

TL;DR: In this article, failure localization in via chain test structures using voltage contrast analysis with SEM/FIB tools and OBIRCH and subsequent destructive failure analysis using FIB/SEM and TEM are described.

TL;DR: In this paper, the effect of modifying the Cu/dielectric cap interface on electromigration EM in dual-damascene interconnect structures is presented, where the Cu surface was treated with reducing NH3,H 2 and reactive SiH4 gases immediately after chemical mechanical polishing, but prior to SiNx dielectric capping.

TL;DR: In this article, an improved behavior in view of electromigration of the metal line was obtained, thereby increasing device reliability by modifying the metal in the vicinity of the interface between the cap layer and metal line.

TL;DR: For successfully developing and controlling BEoL structures of the 32 nm CMOS technology node and beyond, advanced analytical techniques are needed for process development and control, for physical failure localization and analysis as well as for the investigation of reliability-limiting degradation mechanisms as discussed by the authors.

TL;DR: In this paper, the authors used photoelectron spectroscopies and X-ray absorption spectroscopy in total electron yield and total fluorescence yield at the Si2p and the O1s edges to address that issue.