In this paper, a new architecture based on an intentional misalignment between the core and shell gate is presented for the nanotube tunnel field-effect transistor (NT-TFET). The misaligned core gate overlaps with the source region and facilitates line tunneling in the core-gate–source overlapped region significantly increasing the band-to-band tunneling (BTBT) rate. Using the calibrated 3-D simulations, we show that the proposed misaligned (MG) NT-TFET outperforms the conventional NT-TFET both in terms of static as well as dynamic performance. The MGNT-TFET exhibits an increased ON-state current by nearly 11 times as compared to the conventional NT-TFET with an ultrasteep subthreshold slope (minimum point subthreshold swing of ~5 mV/dec and an average subthreshold slope of 15.5 mV/dec). The higher effective drive current also leads to an improved dynamic performance in the MGNT-TFET

A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs

Single-cell RNA-seq (scRNASeq) has become a powerful technique for measuring the transcriptome of individual cells. Unlike the bulk measurements that average the gene expressions over the individual cells, gene measurements at individual cells can be used to study several different tissues and organs at different stages. Identifying the cell types present in the sample from the single cell transcriptome data is a common goal in many single-cell experiments. Several methods have been developed to do this. However, correctly identifying the true cell types remains a challenge. We present a framework that addresses this problem. Our hypothesis is that the meaningful characteristics of the data will remain despite small perturbations of data. We validate the performance of the proposed method on eight publicly available scRNA-seq datasets with known cell types as well as five simulation datasets with different degrees of the cluster separability. We compare the proposed method with five other existing methods: RaceID, SNN-Cliq, SINCERA, SEURAT, and SC3. The results show that the proposed method performs better than the existing methods.

/pdf/identification-of-cell-types-from-single-cell-data-using-1svoo56zis.pdf

Identification of cell types from single cell data using stable clustering.

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

/pdf/a-novel-dopingless-fin-shaped-sige-channel-tfet-with-2vgkxv12d5.pdf

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance.

Based on the nonequilibrium Green’s function (NEGF) ballistic transport simulation, an optimized homojunction carbon nanotube (CNT) gate-all-around tunnel field effect transistor (GAA TFET) is proposed in this study. This TFET enhances the ON-state current and suppresses the ambipolarity extensively. By changing the channel diameter, gate length, and insulator thickness along with different values of doping levels and dielectrics of the source/channel/drain regions, a subthreshold swing $({SS})$ equal to ${11} ~\text {mV}/\text {dec}$ with an ON/OFF ratio of 108 is obtained at ${V}_{G}={V}_{D}={0.4}$ V. Source (drain) underlap/overlap with the gate is also considered in reaching an optimum result. Such advantages can be followed on other 1-D TFET devices and are explained in detail on the energy band diagram of the device.

GAA CNT TFETs Structural Engineering: A Higher ON Current, Lower Ambipolarity

All cellular structures are heterogeneous. Thus, investigating true cell heterogeneity is highly required to further understand cellular connectivity and accountability within a disease or normal conditions. Because of its rapidly decreasing costs, the Next-Generation (NGS) sequence is widely used to analyze various biological data. However, these approaches may fail to provide detailed insight into cells’ true heterogeneity. Recently developed single-cell RNA sequencing (scRNA-seq) technology tries to tackle these bulk NGS issues by linking transcriptomic, epigenomic, proteomic, and molecular sequences to a specific cell. Thus, in this chapter, the author addresses the process involved, relative strengths, possible uses, and limitations of scRNA-seq techniques methods. Information obtained revealed that cell isolation methods may be broadly divided into two categories centered on different principles. The first category centered on physical characteristics, while the second category mainly focuses on cell’ features and primarily involves affinity approaches. After obtaining raw data, the general approach for analyzing ScRNA-Seq data are pre-processing, batch effect correction, normalization, dimensionality reduction, feature selection, cell type identification, differential expression analysis, and rebuilding cell hierarchy. scRNA-seq technologies are continuously being employed to unmask various biological processes ranging from epigenetic regulation to biomarker identification. However, scRNA-seq technologies do have difficulties like cumbersome activity and high detection costs that restrict technology promotion. Hence, there is an urgent requirement to develop more robust tools so that, in the near future, the technology for single-cell sequencing will be streamlined and is more efficient.

Single-Cell RNA Sequencing Technologies

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches $1.44 \times 10^{-6}$ A/ $\mu \text{m}$ of on current and $3.22 \times 10^{9}$ ON/ OFF current ratio. A minimum subthreshold swing SS $_{{\textsf {min}}} = 28.3$ mV/dec and an average swing SS $_{{\textsf {avg}}} = 59.8$ mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of $\textsf {NM}_{H} = 65$ mV (38.5 % $V_{{\textsf {DD}}}$ ) and NM $_{L} = 77$ mV (32.5 % $V_{{\textsf {DD}}}$ ) and also a high voltage gain even at $V_{{\textsf {DD}}} = 0.2$ V.

Characteristics of Recessed-Gate TFETs With Line Tunneling

We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure.

A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gate-control depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of $33.6~\mu \text{A}/\mu \text{m}$ when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application.

Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application

We propose a novel non-classical complementary metal oxide semiconductor (CMOS) inverter, which is composed of a Gated control NNP for driver N-type transistor (Gated-NNP) and a Gated control PPN for load P-type transistor (Gated-PPN). These two transistors have the same doping architecture with tunnel field effect transistor (TFET), but not use tunneling current mechanisms to achieve complementary characteristics. Our Gated-NNP/PPN CMOS inverter exhibits the propagation delay time (TP) 55% lower than the conventional CMOS inverter. Besides, the layout area of the novel inverter is significantly reduced about 46.1% when compared with the conventional CMOS inverter due to the new inverter possesses a unique shared-contacting output node.

A novel low bias and high speed non-classical CMOS inverter with unique shared contact

In this paper, we present a novel non-classical NMOS transistor with elevated body and spacer to replace the conventional PMOS for CMOS circuits. By calibrating the parameters from the real measurement for the simulations, the novel non-classical NMOS transistor shows a PMOS-like behavior. The proposed unipolar CMOS can reduce the propagation delay time (T P ) and power dissipation (P D ). The simulation results show that the T P and P D of the unipolar CMOS circuit are 46% and 20% lower than the conventional CMOS inverter. It has been confirmed that the proposed unipolar CMOS can work well for all NOR logic gates, NAND logic gates, ring oscillator and static random-access memory (SRAM) under 0.5V power supply. Thus, the unipolar CMOS is expected as a candidate for low-power application in near future CMOS technology.

Wei-Han Lee

Papers

Characteristics of Recessed-Gate TFETs With Line Tunneling

A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage

Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application

A novel low bias and high speed non-classical CMOS inverter with unique shared contact

An improved unipolar CMOS with elevated body and spacer for low-power application