Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

High-voltage ICs (HVICs) are used in many applications, including ac/dc conversion, off-line LED lighting, and gate drivers for power modules. This paper describes the technologies most commonly used in commercial HVICs, including junction-isolation, thin silicon-on-insulator (SOI), and thick SOI approaches. Emerging technologies such as thin silicon membrane are also discussed.

High-Voltage Integrated Circuits: History, State of the Art, and Future Prospects

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI) Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced Moreover, the Si window alleviates the self-heating effect The influences of the structure parameters on device characteristics are analyzed for the proposed device structure The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 87 K in comparison with the conventional SOI and partial SOI devices

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage device with a compound buried layer (CBL SOI) consisting of two oxide layers and a polysilicon layer between them is proposed. Its breakdown characteristic is investigated theoretically and experimentally. Theoretically, its vertical breakdown voltage (BV) is shared by two oxide layers; furthermore, the electric field in the lower buried oxide layer of EI2 is increased from about 78 to 454 V/mum by holes collected on the bottom interface of the polysilicon. Both result in an enhanced BV. Experimentally, 762-V SOI diode is obtained. The maximal temperature of CBL SOI diode is reduced by 16.9 K because a window in the upper buried oxide layer alleviates the self-heating effect.

Realization of High Voltage ( $≫ \hbox{700}$ V) in New SOI Devices With a Compound Buried Layer

A novel silicon-on-insulator (SOI) high-voltage device structure with double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in this letter. Theoretically, the charges implemented in the DTs, whose density changes with the drain voltage, increase the electric field in the buried layer and modulate the electric field in the drift region, which results in the enhancement of the breakdown voltage (BV). Experimentally, the BV of 730 V is obtained for the first time in SOI LDMOS with DT on 20-mum SOI layer and 1- mum buried oxide layer

A Novel 700-V SOI LDMOS With Double-Sided Trench

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-k dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low k value, the electric field strength in the buried dielectric (Ej) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific ON-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE.

Partial SOI Power LDMOS With a Variable Low- $k$ Dielectric Buried Layer and a Buried P Layer

A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-k dielectric (LK PSOI) is proposed. The low-k value enhances the electric field strength in the dielectric (EI). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the EI and BV of LK PSOI with kI = 2 are enhanced by 74% and 19%, respectively.

Novel Low- $k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

In this paper, a new push–pull pFLASH switch is designed and fabricated based on a 110 nm eFLASH process, which includes two 2 T-pFLASH transistors and one signal transmission transistor. The pFLASH transistors are programmed and erased by band-to-band tunneling-induced hot electron and Fowler–Nordheim tunneling to realize its ‘on/off’ function, and the current of the signal transmission transistor can be effectively tuned by the drain voltage of the 2 T-pFLASH. In order to clarify the degradation mechanism of the electronic properties, first principles calculations are performed from the atomic scale. Nitrogen vacancies have been proven to play a crucial role in nitrides. In addition, the effects of vacancies on the charge retention are investigated in terms of electronic structure. The nitrogen vacancies have proven to be detrimental to the electron storage by the simulated localization energies. Therefore, this study will provide a newly designed field-programmable gate array configuration unit, whose electrical mechanisms are revealed by theoretical simulations, which can also become the design foundation for future FLASH switches.

Yong Liu

Papers

A Novel 700-V SOI LDMOS With Double-Sided Trench

Partial SOI Power LDMOS With a Variable Low- $k$ Dielectric Buried Layer and a Buried P Layer

Novel Low- $k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

Combined experimental and theoretical investigation on SONOS pFLASH switch