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Yongxun Liu
Researcher at National Institute of Advanced Industrial Science and Technology
Publications - 135
Citations - 1745
Yongxun Liu is an academic researcher from National Institute of Advanced Industrial Science and Technology. The author has contributed to research in topics: Field-effect transistor & MOSFET. The author has an hindex of 20, co-authored 134 publications receiving 1663 citations.
Papers
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Journal ArticleDOI
Demonstration, analysis, and device design considerations for independent DG MOSFETs
M. Masahara,Yongxun Liu,Kunihiro Sakamoto,Kazuhiko Endo,Takashi Matsukawa,K. Ishii,Toshihiro Sekigawa,Hiromi Yamauchi,Hisao Tanoue,Seigo Kanemaru,Hanpei Koike,Eiichi Suzuki +11 more
TL;DR: In this paper, a comprehensive study on the controllability of four-terminal-driven double-gate (DG) MOSFETs with independently switched DGs is presented.
Journal ArticleDOI
A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel
Yongxun Liu,M. Masahara,K. Ishii,Toshihiro Sekigawa,H. Takashima,Hiromi Yamauchi,Eiichi Suzuki +6 more
TL;DR: In this article, an orientation-dependent wet-etching technique was used to verify the controllability of high threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness.
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Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication
Yongxun Liu,S. Kijima,E. Sugimata,M. Masahara,Kazuhiko Endo,Takashi Matsukawa,K. Ishii,Kunihiro Sakamoto,Toshihiro Sekigawa,Hiromi Yamauchi,Y. Takanashi,Eiichi Suzuki +11 more
TL;DR: In this article, a conformal TiN deposition on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering has been demonstrated, where the work function of the TiN (phiTiN) slightly decreases with increasing nitrogen (N2) gas flow ratio, from 17% to 100%.
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Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching
TL;DR: In this article, a Si-Fin channel double-gate MOSFET with smooth [110]-oriented sidewalls was fabricated for the first time using orientation-dependent wet etching, and the transconductance (g/sub m) normalized by 2/spl times/(Fin height) was found to be as high as 700 /spl mu/S/S//spl m/m at V/sub d/=1 V in the fabricated 13nm-thick and 82nm-high Si- Fin channel double gate MOS FET with a 105-
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Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching
M. Masahara,Yongxun Liu,Shinichi Hosokawa,Takashi Matsukawa,K. Ishii,Hisao Tanoue,Kunihiro Sakamoto,Toshihiro Sekigawa,Hiromi Yamauchi,Seigo Kanemaru,Eiichi Suzuki +10 more
TL;DR: In this paper, a vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET was proposed, where the ion-bombardment-retarded etching (IBRE) was used to reduce the channel thickness.