A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

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A SPAD-Based QVGA Image Sensor for Single-Photon Counting and Quanta Imaging

The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture.

The Quanta Image Sensor: Every Photon Counts.

An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2.

A 28-nm 75-fs rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

This paper presents a robust, low-power and compact ion-sensitive field-effect transistor (ISFET) sensing front-end for pH reaction monitoring using unmodified CMOS. Robustness is achieved by overcoming problems of DC offset due to trapped charge and transcoductance reduction due to capacitive division, which commonly exist with implementation of ISFETs in CMOS. Through direct feedback to the floating gate and a low-leakage switching scheme, all the unwanted factors are eliminated while the output is capable of tracking a pH reaction which occurs at the sensing surface. This is confirmed through measured results of multiple devices of different sensing areas, achieving a mean amplification of 1.28 over all fabricated devices and pH sensitivity of 42.1 mV/pH. The front-end is also capable of compensating for accumulated drift using the designed switching scheme by resetting the floating gate voltage. The circuit has been implemented in a commercially-available 0.35 $\mu$ m CMOS technology achieving a combined chemical and electrical output RMS noise of 3.1 mV at a power consumption of 848.1 nW which is capable of detecting pH changes as small as 0.06 pH.

A Robust ISFET pH-Measuring Front-End for Chemical Reaction Monitoring

Several Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are designed, manufactured, characterized and exposed biased to ionizing radiation up to 10 kGy(SiO2 ). In addition to the usually reported dark current increase and quantum efficiency drop at short wavelengths, several original radiation effects are shown: an increase of the pinning voltage, a decrease of the buried photodiode full well capacity, a large change in charge transfer efficiency, the creation of a large number of Total Ionizing Dose (TID) induced Dark Current Random Telegraph Signal (DC-RTS) centers active in the photodiode (even when the Transfer Gate (TG) is accumulated) and the complete depletion of the Pre-Metal Dielectric (PMD) interface at the highest TID leading to a large dark current and the loss of control of the TG on the dark current. The proposed mechanisms at the origin of these degradations are discussed. It is also demonstrated that biasing (i.e., operating) the PPD CIS during irradiation does not enhance the degradations compared to sensors grounded during irradiation.

Radiation Effects in Pinned Photodiode CMOS Image Sensors: Pixel Performance Degradation Due to Total Ionizing Dose

For low-light-level imaging, the performance of a CMOS image sensor (CIS) is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure [1]. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier [2] or a correlated multiple sampling (CMS) technique [3–5]. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches [2–5], and the low-frequency noise of the in-pixel source follower i.e. 1/fand RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.

A 0.7e − rms -temporal-readout-noise CMOS image sensor for low-light-level imaging

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order $\Delta \Sigma $ -TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73–3.38 GHz (after a $\div $ 2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than −110-dBc/Hz in-band PN and occupies an active area of 0.5 mm2. With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fs $_{{\mathrm{rms}}}$ jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the results show that, compared with a regular imager with the standard nMOS transistor surface-mode SF, the new pixel structure reduces dark random noise by 50% and improves the output swing by almost 100% without any conflicts to the signal readout operation of the pixels. Furthermore, the new pixel structure is able to drastically minimize in-pixel random-telegraph-signal noise.

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A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

This paper presents a low-noise CMOS image sensor using column-parallel high-gain signal readout and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as detector. The test sensor has been fabricated in a 0.18 μm CMOS image sensor process from TSMC. The random noise from the pixel readout chain is reduced in two stages, first using a high gain column parallel amplifier and second by using the digital CMS technique. The dark random noise measurement results show that the proposed column-parallel circuits with digital CMS technique is able to achieve 127 μVrms input referred noise. The significant reduction in the sensor read noise enhances the sensor's signal-to-noise ratio (SNR) with 10.4 dB. Such sensors are very attractive for low-light imaging applications which demand high SNR values.

Column-Parallel Digital Correlated Multiple Sampling for Low-Noise CMOS Image Sensors

Low-power, low phase noise (PN) cryogenic frequency generation is required for the control electronics of quantum computers. To avoid limiting the performance of quantum bits, the frequency noise of a PLL should be < 1.9 kHz rms [1]. However, it is challenging for RF oscillators, as the heart of frequency synthesizers to satisfy such a requirement at cryogenic temperatures (CT), since 1) white noise in nanoscale CMOS devices is limited by temperature-independent shot noise; 2) the transistor 1/f noise is much higher, resulting in the oscillator PN being dominated by the 30dB/dec region [1].

Yue Chen

Papers

A 0.7e − rms -temporal-readout-noise CMOS image sensor for low-light-level imaging

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

Column-Parallel Digital Correlated Multiple Sampling for Low-Noise CMOS Image Sensors

19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications