High-performance graphene transistors for radio frequency applications have received much attention and significant progress has been achieved. However, devices based on large-area synthetic graphene, which have direct technological relevance, are still typically outperformed by those based on mechanically exfoliated graphene. Here, we report devices with intrinsic cutoff frequency above 300 GHz, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material. We also demonstrate devices with optimized architecture exhibiting voltage and power gains reaching 20 dB and a wafer-scale integrated graphene amplifier circuit with voltage amplification.

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State-of-the-art graphene high-frequency electronics.

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

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Noise modeling for RF CMOS circuit simulation

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

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A capacitor cross-coupled common-gate low-noise amplifier

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization issues for emerging reconfigurable multiband/multistandard and wideband transceivers. Furthermore, we highlight the impact of CMOS technology scaling on linearity and outline how to design a linear LNA in a deep submicrometer process. Finally, general design guidelines for high-linearity LNAs are provided.

Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

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MOS transistor modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model The procedures of the HF model parameter extraction are also developed A subcircuit RF model based on the discussed approaches can be developed with good model accuracy Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise The distortion behavior of MOSFET and modeling are also discussed The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction

MOSFET modeling for RF IC design

An extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise (i~/sub d/~/sup 2/~), and their cross correlation (i~/sub g/~i~/sub d/~*~) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-/spl mu/m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.

Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements

Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.

Device Modeling for Analog and RF CMOS Circuit Design

High-frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. A subcircuit RF model incorporating the HF effects of parasitics is presented. This model is compared with the measured data for both y parameter and f/sub T/ characteristics. Good model accuracy is achieved against measurements for a 0.25 /spl mu/m RF CMOS technology. The HF noise predictivity of the model is also examined with measured data. Furthermore, a methodology to extract the channel thermal noise of MOSFETs from HF noise measurements is presented. By using the extracted channel thermal noise, any thermal noise models can be verified directly. Several noise models including the RF model discussed in this paper have been examined, and the results show that the RF model can predict the channel thermal noise better than the other models.

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Yuhua Cheng

Papers

MOS transistor modeling for RF IC design

MOSFET modeling for RF IC design

Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements

Device Modeling for Analog and RF CMOS Circuit Design

High-frequency small signal AC and noise modeling of MOSFETs for RF IC design