Journal ArticleDOI
MOSFET modeling for RF IC design
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TLDR
In this paper, a high-frequency (HF) modeling of MOSFETs for radiofrequency (RF) integrated circuit (IC) design is discussed by accounting for important physical effects at both dc and HF.Abstract:
High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model The procedures of the HF model parameter extraction are also developed A subcircuit RF model based on the discussed approaches can be developed with good model accuracy Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise The distortion behavior of MOSFET and modeling are also discussed The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extractionread more
Citations
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Journal ArticleDOI
State-of-the-art graphene high-frequency electronics.
Yanqing Wu,Keith A. Jenkins,Alberto Valdes-Garcia,Damon B. Farmer,Yu Zhu,Ageeth A. Bol,Christos D. Dimitrakopoulos,Wenjuan Zhu,Fengnian Xia,Phaedon Avouris,Yu-Ming Lin +10 more
TL;DR: D devices with intrinsic cutoff frequency above 300 GHz are reported, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material.
Journal ArticleDOI
High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues
TL;DR: In this paper, the most important high-frequency (HF) noise sources of the MOSFETs are modeled, along with challenges in noise measurement and de-embedding of future CMOS technologies.
Journal ArticleDOI
An ultra clean self-aligned process for high maximum oscillation frequency graphene transistors
TL;DR: In this paper, an ultra clean self-aligned graphene transistors fabrication by pre-deposition of gold film on graphene as protection layer is reported, which shows good gate coupling and less parasitics, thus good dc and RF performances.
Journal ArticleDOI
A 3–5 GHz Current-Reuse $g_{m}$ -Boosted CG LNA for Ultrawideband in 130 nm CMOS
M. Khurram,S. M. R. Hasan +1 more
TL;DR: This paper presents a low-power CMOS transconductance “gm” boosted common gate (CG) ultrawideband (UWB) low noise amplifier (LNA) architecture, operating in the 3-5 GHz range, employing current-reuse technique, utilizes a common source (CS) amplifier as the gm-boosting stage which shares the bias current with the CG amplifying stage.
Journal ArticleDOI
Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation
TL;DR: It is demonstrated that methods that convert the MOSFET's input impedance to 50 Omega for power matching are more suitable for low-power applications than methods that create a real 50-Omega resistance at the input of the LNA, such as source inductive degeneration.
References
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TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
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An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications
TL;DR: In this article, a fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented, which exploits the inherent symmetry of the device by referring all the voltages to the local substrate.
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Noise in solid state devices and circuits
TL;DR: In this paper, the authors propose a method to generate 1/f noise noise in particular Amplifier Circuits Mixers by using thermal noise shot and flicker noise, respectively.
Proceedings ArticleDOI
An improved de-embedding technique for on-wafer high-frequency characterization
TL;DR: In this paper, an improved correction procedure for on-wafer S-parameter measurements has been developed and implemented, which takes the effects of series parasitics into account in a simple, straightforward way.