Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Organic (opto)electronic materials have received considerable attention due to their applications in thin-film-transistors, light-emitting diodes, solar cells, sensors, photorefractive devices, and many others. The technological promises include low cost of these materials and the possibility of their room-temperature deposition from solution on large-area and/or flexible substrates. The article reviews the current understanding of the physical mechanisms that determine the (opto)electronic properties of high-performance organic materials. The focus of the review is on photoinduced processes and on electronic properties important for optoelectronic applications relying on charge carrier photogeneration. Additionally, it highlights the capabilities of various experimental techniques for characterization of these materials, summarizes top-of-the-line device performance, and outlines recent trends in the further development of the field. The properties of materials based both on small molecules and on conjug...

Organic Optoelectronic Materials: Mechanisms and Applications

Recent developments in paper-based microfluidic devices.

A comprehensive review on the development and state of the art of colorimetric and fluorometric sensor arrays is presented Chemical sensing aims to detect subtle changes in the chemical environment by transforming relevant chemical or physical properties of molecular or ionic species (ie, analytes) into an analytically useful output Optical arrays based on chemoresponsive colorants (dyes and nanoporous pigments) probe the chemical reactivity of analytes, rather than their physical properties (eg, mass) The chemical specificity of the olfactory system does not come from specific receptors for specific analytes (eg, the traditional lock-and-key model of substrate-enzyme interactions), but rather olfaction makes use of pattern recognition of the combined response of several hundred olfactory receptors In a similar fashion, arrays of chemoresponsive colorants provide high-dimensional data from the color or fluorescence changes of the dyes in these arrays as they are exposed to analytes This provides chemical sensing with high sensitivity (often down to parts per billion levels), impressive discrimination among very similar analytes, and exquisite fingerprinting of extremely similar mixtures over a wide range of analyte types, in both the gas and liquid phases Design of both sensor arrays and instrumentation for their analysis are discussed In addition, the various chemometric and statistical analyses of high-dimensional data (including hierarchical cluster analysis (HCA), principal component analysis (PCA), linear discriminant analysis (LDA), support vector machines (SVMs), and artificial neural networks (ANNs)) are presented and critiqued in reference to their use in chemical sensing A variety of applications are also discussed, including personal dosimetry of toxic industrial chemical, detection of explosives or accelerants, quality control of foods and beverages, biosensing intracellularly, identification of bacteria and fungi, and detection of cancer and disease biomarkers

The Optoelectronic Nose: Colorimetric and Fluorometric Sensor Arrays.

https://www.cell.com/trends/biotechnology/pdf/S0167-7799(15)00187-0.pdf

Emerging Technologies for Next-Generation Point-of-Care Testing

Optical imaging of nanoscale objects, whether it is based on scattering or fluorescence, is a challenging task due to reduced detection signal-to-noise ratio and contrast at subwavelength dimensions. Here, we report a field-portable fluorescence microscopy platform installed on a smart phone for imaging of individual nanoparticles as well as viruses using a lightweight and compact opto-mechanical attachment to the existing camera module of the cell phone. This hand-held fluorescent imaging device utilizes (i) a compact 450 nm laser diode that creates oblique excitation on the sample plane with an incidence angle of ∼75°, (ii) a long-pass thin-film interference filter to reject the scattered excitation light, (iii) an external lens creating 2× optical magnification, and (iv) a translation stage for focus adjustment. We tested the imaging performance of this smart-phone-enabled microscopy platform by detecting isolated 100 nm fluorescent particles as well as individual human cytomegaloviruses that are fluor...

/pdf/fluorescent-imaging-of-single-nanoparticles-and-viruses-on-a-11fx06bejn.pdf

Fluorescent Imaging of Single Nanoparticles and Viruses on a Smart Phone

Computational microscopy tools, in particular lensfree on-chip imaging, provide a large field-of-view along with a long depth-of-field, which makes it feasible to rapidly analyze large volumes of specimen using a compact and light-weight on-chip imaging architecture. To bring molecular specificity to this high-throughput platform, here we demonstrate the use of plasmon-resonant metallic nanoparticles to automatically recognize different cell types based on their plasmon-enhanced lensfree holograms, detected and reconstructed over a large field-of-view of e.g., ~24 mm2.

/pdf/on-chip-cytometry-using-plasmonic-nanoparticle-enhanced-sp39vh5zw0.pdf

On-chip cytometry using plasmonic nanoparticle enhanced lensfree holography.

Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.

Charge-Trap Transistors for CMOS-Only Analog Memory

At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (<100 µm die spacing). The Si-IF platform can accommodate an entire 50 kW data center on a single 300 mm diameter wafer. Power delivery and heat extraction are fundamental challenges. To minimize the overhead of power conversion, current at mission (point-of-load) voltage is planned to be delivered directly to the assembly; this requires a uniform delivery of tens of kilo-amperes. Our approach is to deliver the current from the back of the Si-IF, using cooled Cu fins and through wafer vias (TWVs), to the front side of the wafer, where the dies are assembled facedown. TWVs are a key component of this power delivery system and are required to penetrate through the entire thickness of the Si-IF (500 - 700 µm). A process for fabrication of large-sized (100 µm diameter) TWVs for the Si-IF is described in this paper. The TWVs are etched in 500 µm Si wafer (aspect ratio of 1:5) and are designed to enable back-side power delivery to the integrated system. Each TWV exhibits a resistance of 1.1 mΩ with an extracted resistivity of 1.73⋅10^-8 Ωm. The scale and performance of these large-sized TWVs supports high current density for power delivery applications.

/pdf/process-development-of-power-delivery-through-wafer-vias-for-1b9twpxrde.pdf

Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric

The Von Neumann architecture, defined by strict and hierarchical separation of memory and processor, has been a hallmark of conventional computer design since the 1940s. It is becoming increasingly unsuitable for cognitive applications, which require massive parallel processing of highly interdependent data. Inspired by the brain, we propose a significantly different architecture characterized by a large number of highly interconnected simple processors intertwined with very large amounts of low-latency memory. We contend that this memory-centric architecture can be realized using 3D wafer scale integration for which the technology is nearing readiness, combined with current CMOS device technologies. The natural fault tolerance and lower power requirements of neuromorphic processing make 3D wafer stacking particularly attractive. In order to assess the performance of this architecture, we propose a specific embodiment of a neuronal system using 3D wafer scale integration; formulate a simple model of brain connectivity including short- and long-range connections; and estimate the memory, bandwidth, latency, and power requirements of the system using the connectivity model. We find that 3D wafer scale integration, combined with technologies nearing readiness, offers the potential for scaleup to a primate-scale brain, while further scaleup to a human-scale brain would require significant additional innovations.

/pdf/toward-human-scale-brain-computing-using-3d-wafer-scale-1gtidoyyj5.pdf

Zhe Wan

Papers

Fluorescent Imaging of Single Nanoparticles and Viruses on a Smart Phone

On-chip cytometry using plasmonic nanoparticle enhanced lensfree holography.

Charge-Trap Transistors for CMOS-Only Analog Memory

Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration