Showing papers in "Analog Integrated Circuits and Signal Processing in 2017"

Floating memristor emulator with subthreshold region

Abstract: Memristor which is recently discovered and known as missing circuit element is an important for memory, nonlinear and neuromorphic circuit designs. Modeling of memristor devices is essential for memristor based circuit design. In this paper, compact memristor which has high memristance value is introduced. The simulations are completed in LTspice program and expected results are obtained applying sinusoidal. Two memristor emulators are connected in serial, in parallel and promising results presented. The simulation results of applying positive pulse train to both of terminals of memristor are showed. The simulations of the proposed emulator showed the expected memristor characteristics.

Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path

Abstract: This study describes the analysis and design of an improved recycling folded cascode using a new input path and positive feedback which simultaneously increases transconductance considerably. The proposed amplifier with bias circuits and CMFB circuit was simulated with the TSMC 90 nm and HSPICE circuit simulator @ 1.2 V. According to the simulation results, the proposed circuit shows 75 dB, 357 MHz and 359 µW as DC gain, GBW and power dissipation respectively. This demonstrates 22 dB gain enhancement and 207 MHz GBW improvement, in comparison to recycling the folded cascode (for same capacitor load and power dissipation). Finally, corners and Monte-Carlo simulations were performed to verify the robustness of the proposed circuit versus process, temperature, supply voltage and device dimension mismatch variations.

Real-time ensemble based face recognition system for NAO humanoids using local binary pattern

Abstract: NAO humanoid robots are being used in many human-robot interaction applications. One of the important existing challenges is developing an accurate real-time face recognition system which does not require to have high computational cost. In this research work a real-time face recognition system by using block processing of local binary patterns of the face images captured by NAO humanoid is proposed. Majority voting and best score ensemble approaches have been used in order to boost the recognition results obtained in different colour channels of YUV colour space, which is a default colour space provided by the camera of NAO humanoid. The proposed method has been adopted on NAO humanoid and tested under real-world conditions. The recognition results were boosted in the real-time scenario by employing majority voting on the intra-sequence decisions with window size of 5. The experimental results are showing that the proposed face recognition algorithm overcomes the conventional and state-of-the-art techniques.

Blind channel estimation for massive MIMO

Abstract: In order to scale with the demand of higher data rates and improved spectral efficiency in next generation wireless communication systems, a large-scale multiple-input and multiple-output (MIMO) technology called massive MIMO has been proposed. In massive MIMO, appropriate signal-to-noise ratio (SNR) values can be achieved by the addition of base station (BS) antennas in place of increasing transmit power. Pilot-based channel estimation is widely used in conventional MIMO systems, where pilot signal sequences are sent from the user terminals (UTs) to the BS to estimate the channel. In massive MIMO-based cellular networks, channel estimation in a given cell will be impaired by the pilot signal sequences transmitted by users in other cells--rendering the addition of antennas or transmit power ineffective. This effect is called pilot contamination. Therefore, pilot-based channel estimation limits the performance of massive MIMO. Semi-blind and blind methods are alternatives to pilot-based channel estimation that perform channel estimation with short pilot signal sequences and without pilot signal sequences, respectively. Blind channel estimation is one of the promising solutions to the pilot contamination problem in massive MIMO. This paper compares, using MATLAB simulations of a cluster-based COST 2100 channel model, the performance of pilot-based, semi-blind, blind, and adaptive-blind channel estimation methods. The pilot contamination effect on different channel estimation methods and how channel estimation methods can be used to overcome pilot contamination are shown. Finally, an adaptive independent component analysis (ICA)-based channel estimation method, which outperforms conventional ICA in terms of computational complexity, is proposed.

Optimum design of a double-tail latch comparator on power, speed, offset and size

Abstract: Transistor sizing is one of the most critical parts of comparator design which has a significant influence on comparator specifications. This paper presents an optimum design of a double-tail latch comparator based on transistor sizing with a great certainty to reach the best possible design due to using Hspice (as a software simulator) linked with a heuristic algorithm. To achieve a low-power, high-speed, low offset and, small size comparator, the multi-objective inclined planes optimization and Hspice were linked and several Pareto-fronts were obtained. As a result of analyzing the Pareto-fronts, power and total sizes of transistors have a tradeoff with delay and offset voltage. Meanwhile, the results comparison with a recent work shows the superiority of the present approach performance.

Erratum to: Design of new practical phase shaping circuit using optimal pole---zero interlacing algorithm for fractional order PID controller

Abstract: This paper presents the implementation of fractional order PID (FO-PID) controller using hardwired modules of constant phase element (CPE). A new approach of phase shaping by slope cancellation of asymptotic phase plots for zeros and poles within the given bandwidth is realized. Analog circuits, which exhibit analog fractional-order integrator and fractional-order differentiator, are used for building the FO-PID controller. The design procedure is developed to obtain the optimal pole---zero pairs and respective "Fractance" components to realize for any value of fractional differ-integrator. These CPE elements give minimum error tolerance over the set phase value by using commercially available (R---C) components and Op-Amps. The pole---zero location in the root locus plot with constant asymptotic angle under various feed-forward gains is achieved with these analog integrodifferential circuits of the FO-PID. The iso-damping feature of the controller is practically demonstrated. A comparative performance is demonstrated under various settings of feed forward gains, which indicate the constant overshoot with FO-PID against the conventional PID. These circuits are developed and implemented with a DC motor emulator to confirm the designed performance of the controller.

A fast training method for memristor crossbar based multi-layer neural networks

Abstract: Memristor crossbar arrays carry out multiply–add operations in parallel in the analog domain which is the dominant operation in a neural network application. On-chip training of memristor neural network systems have the significant advantage of being able to get around device variability and faults. This paper presents a novel technique for on-chip training of multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed system utilizes a novel variant of the back-propagation (BP) algorithm to reduce both circuit area and training time. During training, all the memristors in a crossbar are updated in four steps in parallel. We evaluated the training of the proposed system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. The proposed training algorithm trained the nonlinearly separable functions with a slight loss in accuracy compared to training with the traditional BP algorithm.

A MOS translinear cell-based configurable block for current-mode analog signal processing

Abstract: This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.

Classification of LPI radar signals using spectral correlation and support vector machines

Abstract: In modern radar systems, low probability of intercept (LPI) waveforms are used to make detection by a potential adversary difficult. This is accomplished using wideband waveforms, frequency hopping, and continuous waveforms (FMCW) to reduce the signal profile. The low signal profile of the LPI signal enables the radar to perform detection and or target tracking while the target remains unaware. Several modulation techniques such as polytime codes, polyphase codes, FSK, and FMCW are used to produce LPI signals for transmission. This paper looks at the ability of spectral correlation along with a support vector machine in order to automatically classify the different LPI signal types in a non-cooperative environment.

New two-CFOA-based floating immittance simulators

Abstract: This paper presents new topologies for emulating floating immittance functions using three to five passive elements and only two current-feedback operational-amplifiers (CFOAs). The feasibility of using only two CFOAs and two passive components is explored. The proposed topologies can emulate lossy positive and negative inductances and capacitance-, inductance-, resistance-multipliers, and frequency dependent negative and positive conductances. The functionality of the proposed circuits was experimentally verified using the commercially available AD844 CFOA. The experimental results are in excellent agreement with theoretical calculations.

Low voltage, high CMRR, and wide bandwidth novel current mode current controlled instrumentation amplifier

Abstract: In this paper, a new current controlled instrumentation amplifier structure is proposed. The introduced circuit uses three current controlled conveyors and a single grounded resistor. This structure offers several enhanced advantages in comparison with other current and voltage modes instrumentation amplifiers. It provides attractive features such as: wide bandwidth independent to the differential gain, current tuned gain, high common mode rejection ratio without requiring matched resistors and low supply voltage equal to ±0.75 V. Accordingly, the proposed amplifier is a suitable element for integrated circuit implementation in the medical field. The used second-generation current controlled conveyor has a very simple structure. It is generally constituted of two NPN and seven CMOS transistors and it has numerous interesting characteristics. Theoretical analysis is carried out taking into consideration the non-ideality parameters of the conveyors. The circuit features are corroborated via a PSPICE simulation; the results are also compared to those of the previous structures presented in the literature.

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

Abstract: The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Abstract: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process.

An efficient approach to enhance bulk-driven amplifiers

Abstract: In this paper, a single-stage class AB bulk-driven amplifier operating in weak inversion region is proposed. The presented amplifier benefits from an improved high input swing structure using quasi-floating-gate technique. The composite transistors and recycling configuration used at the input stage enable the input differential pair to operate under low supply voltages with larger transconductance as compared to the conventional models at no expense of power budget. The circuit is designed in 0.18 µm CMOS technology and simulation results show 61.5 dB low frequency gain with the gain bandwidth of 30.15 kHz and 55.3 V/ms average slew rate. The total current of 275 nA and 0.6 V supply voltage make the proposed amplifier a suitable choice for ultra-low-power applications.

A 0.1–1.1 GHz inductorless differential LNA with double g m -boosting and positive feedback

Abstract: A 0.1–1.1 GHz wideband low-noise amplifier (LNA) is proposed in this paper. The LNA is a fully differential common-gate structure. Large equivalent transconductance $$(g_m)$$ is realized by active $$g_m$$ -boost and capacitive cross-coupling. By introducing a positive feedback path, the circuit increases design freedom. It alleviates the tradeoff between input matching, gain and noise performance. The proposed LNA avoids the use of on-chip inductors to save area and cost. A prototype is implemented in standard TSMC 180-nm CMOS technology. From the measurement, the proposed LNA shows a 19 dB voltage gain with a 1 GHz 3-dB bandwidth. The minimum noise figure (NF) is 3.1 dB. The LNA achieves a return loss greater than 10 dB across the entire band and the third-order input-referred intercept (IIP3) is better than $$-\,2.9$$ dBm. The core consumes 3.8 mW from 1-V supply occupying an area of 0.03 $$\hbox {mm}^2$$ .

A new compact CMOS C-multiplier

Abstract: This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the translinear principle with MOSFETs operating in subthreshold region. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator was used to confirm the functionality of the design in 0.18 µm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor can be varied from 10 to 300. The functionality of the proposed capacitance multiplier was demonstrated by using it in designing a low pass filter and a relaxation oscillator.

ZigBee-based indoor localization system with the personal dynamic positioning method and modified particle filter estimation

Abstract: We introduce a portable Wireless Sensor Network; which characterized by its great precision, fast detection, real time-monitoring and cheapness. The received signal strength indication (RSSI) is used for estimating the location of the target based on the trilateration algorithm. One of the biggest issues when acquiring a precise location is the numerous calculations that are required within particle filtering. Therefore, we have suggested a modified particle filtering (MPF) using a ZigBee model; in order to minimize both error and huge computations within the indoor environment based on the variance and gradient data-resampling. Increasing the particle weight near the estimated position using RSSI localization helps in avoiding undesired estimations. The MPF algorithm has been enhanced to predict a moving target within an indoor location with an average accuracy of approximately 1.5–2 m while consuming less power. The efficient number of particles has been improved, in addition to the estimated error; in comparison to the classical methods. The results prove that our algorithm can effectively meet the general indoor environmental demands with significant improvements over other algorithms and good position’s evaluation.

LSB split capacitor SAR ADC with 99.2% switching energy reduction

Abstract: A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

Abstract: This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).

Making use of semiconductor manufacturing process variations: FinFET-based physical unclonable functions for efficient security integration in the IoT

Abstract: In a typical design environment, semiconductor manufacturing variations are considered as challenges for nanoelectronic circuit design engineers. This has led to multi-front research on process variations analysis and its mitigations. As a paradigm shift of that trend the present article explores the use of semiconductor manufacturing variations for enhancing security of systems using FinFET technology as an example. FinFETs were introduced to replace high-$$\kappa $$ź transistors in nanoelectronic applications. From microprocessors to graphic processing units, FinFETs are being used commercially today. Along with the technological advancements in computing and networking, the number of cyber attacks has also increased. Simultaneously, numerous implementations of the Internet of Things are already present. In this environment, one small security flaw is enough to place the entire network in danger. Encrypting communications in such an environment is vital. Physical unclonable functions (PUFs) can be used to encrypt device to device communications and are the main focus of this paper. PUFs are hardware primitives which rely on semiconductor manufacturing variations to generate characteristics which are used for this purpose. Two different designs of a ring oscillator PUF are introduced, one with low power consumption trading off device performance and one high-performance trading off device power consumption. There is an 11% decrease in power consumption with the low power model along with a simple design and fabrication. Performance of the device can be increased with almost no increase in power consumption.

Low power ring oscillator for IoT applications

Abstract: This paper proposes a low power ring oscillator by combining current starving technique with negative skewed delay approach. This design has shown an improvement of more than 50% in the power delay product compared to the state of the art techniques. Circuit simulations are carried out in standard 65 nm technology. The proposed circuit has shown a robust performance against temperature and voltage variation within 10%. Therefore this circuit can find potential applications in IoT devices and RFID tags operating from 10 MHz to 1 GHz.

FVF LDO regulator with dual dynamic-load composite gain stage

Abstract: A low-voltage output-capacitorless low-dropout regulator using dual dynamic-load composite gain stage for flipped voltage follower topology is presented. It also incorporates a delay discharge circuit which aims to reduce the long discharge time arising from the large capacitive load, thus achieving the overshoot time reduction and sustaining fast transient characteristic when driving low-power digital system with internal heavy capacitive load requirement. The regulator can support a minimum of 0.75 V input voltage with 0.5 V output voltage. It consumes 49.4 µA whilst maintaining the stability for a capacitance load range from 470 pF to 10 nF. For a current load transient from 0 to 10 mA with 200 ps edge time, the settling time is 0.38 µs for the load capacitance of 3 nF. The obtained transient figure-of-merit is 0.42 mV. This transient metric outperforms the representative prior-art reported works.

A novel 9T SRAM architecture for low leakage and high performance

Abstract: A novel 9T-SRAM architecture is proposed in this paper It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell The proposed cell consists of nine transistors with separate read/write ports It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 6607 and 1051% respectively Again, the write delay is reduced to about 95% while read delay is minimized to about 641% under different body-bias voltages

Lossless grounded FDNR simulator and its applications using OTRA

Abstract: In this paper, a new grounded positive lossless frequency dependent negative resistance (FDNR) simulator and two of its applications are presented. The proposed FDNR uses single OTRA and requires five number of passive components; two resistances and three capacitances. The workability of the proposed simulator is demonstrated through the realization of a single resistance controlled oscillator (SRCO) and a fifth order elliptic filter. A detail non-ideality analysis is also done for both FDNR and SRCO. In addition the sensitivity, non-ideality effect and frequency stability analysis of SRCO have been presented. Monte Carlo simulation of the SRCO output has been given and discussed. Moreover, the layout of OTRA, FDNR and SRCO and their post layout simulations in 180 nm are given. PSPICE simulation and experimental results are included to verify theory.

Energy-efficient switching scheme for ultra-low voltage SAR ADC

Abstract: An energy-efficient capacitor switching scheme for ultra-low voltage successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The novel switching scheme uses two reference levels, which eliminates the dependency on the accuracy of the extra reference voltage (Vcm). In addition, the proposed scheme combines merge-and-split (MS) switching method, floating switching method and LSB-down switching method. More switching energy is saved with switching energy optimization before the third comparison, and the number of capacitors in the capacitor array is also reduced by 75% due to LSB-down switching method. The proposed scheme achieves a 98.4% reduction in switching energy when compared with the conventional SAR architecture.

A new CMOS comparator robust to process and temperature variations for SAR ADC converters

Abstract: This paper presents a novel comparator being robust to temperature and process variations. The new comparator is confronted to a conventional topology used in most of the Successive Approximations Analog to Digital Converters (SAR ADCs) for biomedical applications. To verify the benefits of the new comparator, it was designed on a CMOS 65 nm process and characterized with post layout simulations under conditions of process and temperature fluctuations. With the proposed circuit, a SAR ADC exhibits 83.11 dB of Signal to Noise Ratio at 1.28 MS/s and $$375\,\upmu\hbox {W}$$375μW of power consumption. The PT variations for critical corners are less than 0.58 bits.

Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

Abstract: This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.

Parametric fault detection of analog circuits based on Bhattacharyya measure

Abstract: This paper presents a fault detection algorithm to detect parametric fault in linear and weakly non-linear analog circuits by Bhattacharyya measure, a statistical metric. Linear feedback shift register (LFSR) generated pseudo-random bit sequences are fed to digital-to-analog converter (DAC) to obtain random analog input stimuli for the circuit under test (CUT). Bhattacharyya coefficient is measured from the probability density function (PDF) of the output. The non-Gaussian auto-regressive model is used to estimate the PDF. Component tolerance is mapped into statistical space by Monte Carlo simulation. The proposed methodology is validated through three benchmark circuits: continuous-time low pass state variable filter circuit, fourth order low pass Chebyshev filter circuit and cascade amplifier. All the circuits are simulated with CADENCE Virtuoso using UMC-180nm technology. Defect screening is also measured with linear regression analysis. Detectability of the proposed method for parametric fault is reasonably large in comparison to functional test method.

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

Abstract: An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (Vcm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.

Variable mode CMOS full-wave rectifier

Abstract: A variable mode full-wave rectifier deploying one MOCCCII (multiple output current controlled conveyor), one CC (current comparator) and analogue switch, without any external passive components and diodes is presented. The circuit supports precise processing of input signals of up to 200 MHz frequency, producing an input operating range of ±150 mV in the voltage mode (VM) and ±300 μA in the current mode (CM). It also exhibits good temperature stability. Signal-processing related errors and errors bound were investigated and presented in the paper. The presented circuit has an appropriate zero crossing performance, linearity and low component count. It is also suitable for monolithic integrated implementation. The simulation results confirm the feasibility of the proposed circuit. The maximum power consumptions of the rectifier at ±1.65 V supply voltages amount to approximately 4.62 mW.