Showing papers in "IEEE Transactions on Electronics Packaging Manufacturing in 2006"

Surface Insulation Resistance of Conformally Coated Printed Circuit Boards Processed With No-Clean Flux

Abstract: Printed circuit board (PCB) specimens containing three different IPC-B-25 test structures were exposed to temperature/humidity/bias conditions in order to evaluate the effects of conformal coating, conductor spacing, voltage bias, flux chemistry, and test environment on surface insulation resistance (SIR). Results indicate that conformal coatings improve reliability, provided that sources of contamination on the PCB and within the coating are minimized. The presence of fibrous contaminants within the coating represented a preferential medium for moisture adsorption and ion transport, leading to accelerated reduction of SIR. In the absence of contamination, PCBs with conformal coatings were found to be less susceptible to SIR degradation than uncoated PCBs, with silicone providing better protection than urethane, and acrylic providing the least protection of the three coating materials evaluated. Conductor spacing was observed to represent a factor in the electrochemical migration (ECM) process independent of electric field, indicating that updated test structures are required to predict reliability of today's high-density assemblies. The SIR failure rate with rosin-based no-clean flux was observed to be greater than that with aqueous-based no-clean flux. A higher failure rate was also observed for tests conducted at 40 degC/93% RH than for 85 degC/85% RH. Due to the more rapid evaporation of weak organic acids in the flux residues at higher temperatures, test results obtained at 85 degC/85% RH will not accurately predict reliability at lower temperatures for PCBs processed using no-clean flux. PCB specimens were exposed to temperature/humidity/bias conditions in order to evaluate the effects of conformal coating, conductor spacing, voltage bias, flux chemistry, and test environment on reduction of surface insulation resistance. Results indicate that, in the absence of contamination, conformal coatings improve reliability

Acid Decapsulation of Epoxy Molded IC Packages With Copper Wire Bonds

Abstract: Epoxy molded IC packages with copper wire bonds are decapsulated using mixtures of concentrated sulfuric acid (20%) and fuming nitric acid in an automatic decapping unit and, observed with minimal corrosion of copper wires (0.8-6 mil sizes) and bond interfaces. To attain maximum cross-linking of the molded epoxies, the post mold cured packages (175 degC for 4 h) were further, aged at high temperature of 150 degC for 1000 h. These packages are decapsulated using mixtures of higher ratio of concentrated sulfuric acid (40%) along with fuming nitric acid. The shear strength of copper wire bonds with 1 mil (25 mum) diameter of the decapsulated unit is higher than 5.5 gf/mil2. The present study shows copper stitch bonds to Au, Cu, Pd, and Sn alloy plated surfaces are less affected on decapping, with a few grams of breaking load on stitch pull test, while stitch bonds on silver plated surfaces reveal lifting of wire bonds on decapping

Fabrication of microvias for multilayer LTCC substrates

Abstract: Advances in screen printing and photoimageable paste technologies have allowed low-temperature cofired ceramic (LTCC) circuit densities to continue to increase; however, the size of vias for Z-axis interconnections in multilayer LTCC substrates have been a limiting process constraint. In order to effectively exploit the 50-100-/spl mu/m line/spacing capabilities of advanced screen printing and photoimageable techniques, microvia technologies need to achieve 100 /spl mu/m and under in diameter. Three main steps in fabrication of microvias include via formation, via metallization or via fill, and layer-to-layer alignment. The challenges associated with the processing and equipment for the fabrication of microvias are addressed in this paper. Microvias down to 50 /spl mu/m in diameter with spacings as small as 50 /spl mu/m are achieved in 50-254-/spl mu/m-thick LTCC tape layers through the use of a mechanical punching system, whereas the minimum size of 75-/spl mu/m via/spacing is obtained using a pulse laser-drilling system in the LTCC tape layers with the same thicknesses as those for the punching test. The quality of punched microvias and laser-drilled microvias will be presented as well. Layer-to-layer alignment is crucial to the connection of vias in adjacent LTCC tape layers. Through a stack and tack machine with a three-camera vision system and an adjustable precision stage, less than 25-/spl mu/m layer-to-layer misalignment is achieved across a 114.3/spl times/114.3 mm (4.5/spl times/4.5 in) design area. In a six-layer LTCC test substrate (152/spl times/152/spl times/0.762 mm), microvias of 50, 75, and 100 /spl mu/m in diameter are successfully fabricated without the use of via catch pads. The cross section of fired microvias filled with silver conductor pastes at various locations of this substrate demonstrates a minor layer-to-layer misalignment in both X and Y directions across the substrate.

Humidity Effects on Sn Whisker Formation

Abstract: Due to legislative issues, Pb-containing metallizations on semiconductor components are rapidly converted to Pb-free alternatives. One of the most popular alternatives is Sn electroplating. The major problem of these platings is the formation of Sn whiskers. In earlier publications, two mechanisms were uncovered that are responsible for whisker growth. However, these mechanisms do not explain whisker growth in high humidity. Therefore, Freescale, Infineon, Philips, and STMicrolectronics (E4) joined forces and started a design of experiment (DoE) in order to resolve this mechanism. It is shown that in high humidities, whiskers grow due to oxidation and corrosion of the Sn plating, irrespective of the base material. It is also shown that board assembly mitigates the whisker growth by this mechanism but does not completely prevent it

Effects of fluid properties on dispensing processes for electronics packaging

Abstract: The fluid dispensing process has been widely employed in electronics packaging manufacturing to deliver fluid materials (such as epoxy, encapsulant, adhesive) on substrates or printed circuit boards (PCBs) for the purpose of die attachment, encapsulation, coating, or surface mounting. In this process, the fluid properties such as How behavior, surface tension, and contact angle can have a significant influence on the How rate of the fluid dispensed and the profile of fluid formed on the substrate or PCB, thereby affecting the quality of electronics packaging. At present, massive measurements are always required to characterize the fluid properties by using specific instruments, and the procedure of measuring is time-consuming. This paper presents a method upon which the fluid properties and their influence on the dispensing process can be readily identified from a few measurements of the process. By experiments, this method was proven to be not only cost and time effective but also promising for the investigation into the effects of fluid properties on the dispensing process.

Full-field 3-D measurement of solder pastes using LCD-based phase shifting techniques

Abstract: Quality inspection of deposited solder pastes is critical in surface mounting processes. As surface-mount technology (SMT) component pitches decrease, three-dimensional (3-D) measurement of solder pastes has become more and more important in ensuring solder joint reliability. Currently, the 3-D measurements for solder pastes are mainly performed by laser-based systems. However, they suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for deposited solder pastes is proposed. The proposed system uses a liquid crystal display (LCD)-based phase shifting technique to perform full-field 3-D measurement of solder pastes with high accuracy. Experiments have shown that the 3-D profiling and volume measurement of solder pastes are very efficient and effective with the proposed system. The volume measurement repeatability is in the micrometer range. The processing time of the proposed 3-D measurement system for an image of 640/spl times/480 pixels is less than 1 s on a typical personal computer.

Planning the e-Scrap Reverse Production System Under Uncertainty in the State of Georgia: A Case Study

Abstract: Due to legislative requirements, environmental concerns, and market image, the disposition of end-of-life e-scrap is attracting tremendous attention in many parts of the world today. Effective management of returned used product flows can have a great impact on the profitability and resulting financial viability of associated e-scrap reverse production systems. However, designing efficient e-scrap reverse production systems is complicated by the high degree of uncertainty surrounding several key factors. Very few examples of this complex design problem are documented in the academic literature. This paper contributes as analysis of a new, large-scale application that designs an infrastructure to process used televisions, monitors, and computer central processing units (CPUs) in the state of Georgia in the U.S. The case study employs a scenario-based robust optimization model for supporting strategic e-scrap reverse production infrastructure design decisions under uncertainty. A mixed integer linear programming (MILP) model is used to maximize the system net profit for specified deterministic parameter values in each scenario, and then a min-max robust optimization methodology finds a robust solution for all of the scenarios

A Statistical Study of Sn Whisker Population and Growth During Elevated Temperature and Humidity Tests

Abstract: Storage tests at elevated temperature and humidity conditions have been widely adopted as one of the major acceleration tests for Sn whisker growth. However, the driving force associated and the nucleation and growth process of whiskers are yet to be fully understood. In this paper, Sn whisker growth on Cu leadframe material at two different test conditions is compared. Both loose and board-mounted components were used. At each read point, the length and location of every whisker observed was recorded. Statistical characteristics and growth rate of the whisker population will be presented for each of the tests conditions. On loose components, corrosion of the Sn finish was observed near the tip and the dam bar cut area of the leads with backscatter scanning electron microscopy (SEM) and optical microscopy. The entire population of whiskers was located in these corroded areas, and there were zero whiskers located in the noncorroded areas on the same leads. On board-mounted components, the corrosion level of the Sn finish, as well as the whisker population and length was greatly reduced compared to those on the loose components. These results suggest that the corrosion of Sn finish in high-temperature and high-humidity conditions is the major driving force for whisker growth. The cause for the difference between the loose and board-mounted components is also analyzed

Multiple Orders Per Job Compatible Batch Scheduling

Abstract: This paper investigates the problem of grouping different customer orders into jobs and these formed jobs to batches and scheduling them on a single batch processing machine to minimize the total weighted tardiness of orders. A compatible batching environment is considered in which there is no restriction on the orders being from the same family to be batched together. A mixed-integer program (MIP) is developed and tested. The compatible MIP model takes 1 + h, on average, to solve an instance. A new simulated annealing-based heuristic solves compatible problems to within 4% of optimality in a few minutes. This fast, near optimal performance suggests that these heuristics may be viable for implementation in practical manufacturing settings, such as burn-in operations in the back end of the semiconductor manufacturing process

Viable plastics recycling from end-of-life electronics

Abstract: Millions of end-of-life (EOL) electronic products represent more than one million tons of engineering thermoplastics. The economically and environmentally sound recovery of engineering thermoplastics from EOL electronics is a challenge to the sustainability of electronics manufacturing. In this paper, we review the technologies to separate and identify pure post-consumer plastics from EOL electronics, which are followed by the comparison of electronic plastics recycling processes and the network models for plastics recycling processes. We also review successful plastics recycling practices for electronics. In addition, further research directions for recycling plastics from EOL electronics are discussed.

Establishing a Relationship Between Warranty and Reliability

Abstract: In today's competitive marketplace, customers have come to expect that the products they purchase will perform as intended, and federal and state laws have been passed to enshrine this as a right of customers. A warranty is a written assurance that the manufacturer of a product will guarantee the quality and reliability of a product in terms of correcting any legitimate problems with the product at no additional cost, for some expressed or implied period of time or use. This paper presents the concept of a warranty, and the relationship between warranty and reliability. The paper is written in the context of the automotive industry, with a case study of an ignition module. A list of best practices and recommendations is provided. One key conclusion is that all warranty as well as out-of-warranty returns be considered field failures unless proven that another cause for returns exist

Tin Whisker Test Method Development

Abstract: The International Electronics Manufacturing Initiative (iNEMI) proposed a set of tests that were subsequently standardized by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association as JESD22A121. However, further optimization was needed to validate and verify proposed iNEMI tests to determine whether these test methods could differentiate between component surface finishes, to investigate the connection between short-term and long-term tests, and to determine optimal inspection intervals and test durations. In the current work, 15 surface finishes were evaluated using iNEMI's three proposed environmental test conditions. These finishes were evaluated for whisker presence and length using a scanning electron microscope (SEM) every 1000 h or 500 accelerated thermal cycles for a total of at least 9000 h of isothermal testing or 3000 accelerated thermal cycles. Test results showed that thermal cycling and high-temperature/humidity testing could grow whiskers for all Pb-free Sn-based finishes, while only a few finishes exhibited whiskers after 10 000 h in an air-conditioned office environment. The results described in this paper were used to change the JEDEC tin whisker test method from the original iNEMI proposal by decreasing the humidity of the high-temperature humidity test, controlling the ambient test condition to 30 degC and 60% relative humidity (RH), and increasing the number of leads per sample and number of samples (sample size) for inspection

Lead-free chip scale packages: assembly and drop test reliability

Abstract: Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.

Online multiobjective Pareto optimal dynamic scheduling of semiconductor back-end using conjunctive simulated scheduling

Abstract: A discrete event simulation based "online near-real-time" dynamic multiobjective scheduling system has been conceptualized, designed, and developed to achieve Pareto optimal solutions in a complex manufacturing environment of semiconductor back-end. Our approach includes the use of linear weighted aggregation optimization approach for multiple objectives and auto simulation model generation for online simulation. Developed concepts are implemented at a semiconductor back-end site and are in use. The impact of the system includes a better customer delivery achievement, consistent cycle time with narrower distribution, improved machine utilization, reduction in the time that planners and manufacturing personnel spend on scheduling, and more predictable and repeatable manufacturing performance. In addition, it enables managers and senior planners to carry out "what now" analysis to make effective current decisions and "what if" analysis to plan for the future.

Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping

Abstract: Thin wafers of 100-/spl mu/m thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass.

Eco-efficiency of take-back and recycling, a comprehensive approach

Abstract: A key question in setting up take-back systems for discarded consumer electronics is how much environmental improvement can be realized per amount of money invested. With the eco-efficiency concept developed, the environmental and economic performance of single products within various end-of-life scenarios can be quantified as well as the contribution of individual materials and material fractions to this performance. Also analysis the effectiveness and efficiency of optimization and changes in the take-back system like, glass recycling and plastic recycling, and Design for End-of-Life activities is determined. Moreover, the environmental effectiveness and cost-efficiency effects of the European Waste of Electrical and Electronic Equipment (WEEE) Directive is reviewed. Based on the eco-efficiency analyses, an implementation roadmap for this legislation is proposed in order to further improve environmental performance on one hand and to minimize costs on the other hand.

Stress-Induced Tin Whisker Initiation Under Contact Loading

Abstract: As electronic components become smaller, tin whiskers have an increasingly adverse effect on the assessment of the reliability of the components. In particular, the contact between components brings about whisker initiation near the contact area. Although a number of spontaneous tin whisker models have been proposed, a model of tin whisker initiation by contact loading has not yet been established. In this paper, the behavior of stress-induced tin whiskering by contact load was examined in a tin plating based on multiaxial creep theory. Creep properties were measured using a nanoindentation creep technique. The creep rate of Sn-10Pb is higher than that of Sn and affects the generation of compressive stresses after stress relaxation. Nonlinear finite-element analysis (FEA) reveals that the multiaxial compressive stress state appears after stress relaxation. The axial compressive stress increases even though the contact stress decreases. When multiaxial stresses are applied, not only axial stress but also the difference between stresses, affects the behavior of whisker formation. The axial compressive stress depends on the structures of the contact bodies, and the contact stress depends on the creep properties of the plating

Reliability Investigation of Mixed BGA Assemblies

Abstract: The effect of different reflow profiles on the reliability of lead-free (LF) Sn-3.0 Ag-0.5 Cu (wt.%) (SAC 305) ball grid array (BGA) devices assembled with a SnPb eutectic paste was investigated. The memory modules in a back-to-back configuration were reflowed on standard graphic cards finished with immersion silver (IAg) or hot air solder leveling (HASL) coatings. The reflow peak temperatures ranged from 209 degC to 227 degC, while the time above liquidus (TAL) varied from 45 to 80 s. Depending on the reflow conditions, the solder interconnects displayed varied degrees of SnPb and LF solders intermixing. It was established that in order to receive a homogeneous solder alloy, the reflow peak temperature had to be in the 218 degC-222 degC range. The reliability of solder interconnects of memory modules was assessed by subjecting the cards to 1500 cycles of accelerated thermal-cycling with a profile from 0 degC to 100 degC. It was found that the control SnPb/SnPb assemblies displayed superior reliability to that of the mixed assemblies. Regardless of the degree of homogeneity of the BGA balls, the predominant failure mode of the mixed solder joints was interfacial cracking through a Pb-rich phase near the intermetallic layer. In contrast, only partial cracks propagating diagonally through the bulk solder were present on the control boards. It was concluded that a combination of state of stress and segregation of the Pb-rich phase at the interface was responsible for the shortened thermal-mechanical fatigue life of the mixed solder interconnects

The Effect of Annealing on Tin Whisker Growth

Abstract: This paper presents a design-of-experiments study on the effect of annealing and simulated reflow on tin whisker growth. Copper, brass, and alloy 42 coupons plated with either bright or matte tin were subjected to one of three elevated temperature exposures. After the elevated temperature exposures, specimens along with a set of control specimens were then kept in room ambient conditions and monitored periodically using an environmentally scanning electron microscope. Surface observations up to 16 months of room ambient exposure revealed that tin whiskers formed on the surfaces of each specimen. However, various differences in whisker growth between the matte- and bright tin-plated specimens were observed. Columnar-type whiskers grown on the matte tin plated specimens were initiated from one grain at the surface, as opposed to the growth on bright tin which were independent from the surface morphology. Maximum length and length distribution data for matte and bright tin plating for the various exposures are presented. The result of this study shows annealing to be effective in reducing the maximum length of whiskers, particularly on bright finished coupons

Characteristics of Sn–Cu Solder Bump Formed by Electroplating for Flip Chip

Abstract: Sn–Cu near eutectic solder bump was fabricated by electroplating for flip-chip, and its electroplating and bump characteristics were studied. A Si-wafer was used as a substrate and the under bump metallization (UBM) comprised 400 nm of Al, 300 nm of Cu, 400 nm of Ni, and 20 nm of Au sequentially from bottom to the top of the metallization. The electrolyte for plating Sn–Cu solder consisted of $hbox Sn^+2$ (concentration of 30 g/L) and $hbox Cu^+2$ (0.3 g/L) solutions with methasulfonic acid and deionized water. The experimental results showed that the plating ratio of the Sn–Cu increased from 0.25 to 2.7 $mu/hbox min$ with increasing current density from 1 to 8 $hbox A/dm^2$ . In this range of current density, the plated Sn–Cu maintained its composition nearly constant level as Sn-(0.9 $sim$ 1.4)wt% Cu. The solder bump of typical mushroom shape with 120- $muhbox m$ stem diameter and 75- $muhbox m$ height was formed by plating at 5 $hbox A/dm^2$ for 2 h. The mushroom bump changed its shape to the hemispherical type of 140- $muhbox m$ diameter by air reflow on a hot plate at 260 $^circhbox C$ . The homogeneity of element distribution in the solder bump was examined, and Sn content in the mushroom bump appears to be uneven changed to more uniform after the air reflow. The highest shear bond strength of the Sn–Cu hemispherical bump showed 113 gf by reflowing at 260 $^circhbox C$ for 10 s.

Wave Soldering Using Sn/3.0Ag/0.5Cu Solder and Water Soluble VOC-Free Flux

Abstract: Environmental and health concerns, due to the leaching of lead from landfills into ground water, have necessitated legislation that restricts the use of lead in electronics. The transition from the eutectic tin-lead composition used in electronic solders to lead-free solder is imminent. Understanding the impact of this transition on lead-free wave soldering is crucial because a large segment of printed circuit boards (PCBs) used in electronic home appliances are wave soldered. The usage of volatile organic compound (VOC)-free flux chemistry is expected to gather momentum in conjunction with lead-free wave soldering because of process requirements and environmental considerations. A thorough review of published literature indicated that there is limited information available on the application of water-soluble VOC-free flux chemistries for lead-free wave soldering. Consequently, the objectives of this research were to select a preferred VOC-free water-soluble flux chemistry, understand the process window of wave soldering using a 96.5Sn/3.0Ag/0.5Cu lead-free alloy, and study the impact of the lead-free wave soldering process on different surface finishes. Many of the earlier process recommendations were based on a solder pot temperature of 260 degC and higher. However, the packaging of through hole components may not withstand the higher pot temperature and longer contact time. Hence, assembly at a lower solder pot temperature and shorter contact time are highly desired. Consequently, experiments were conducted to verify the feasibility of reducing the solder pot temperature (250 degC) and the contact time (2 s). Three VOC-free fluxes, from three different vendors, were evaluated and the best flux chosen was used to establish the process window. It was demonstrated through this study that it is possible to wave solder, using a lead-free solder with low silver content, different surface finishes with a wide process window. The effect of lead-free process temperatures on the cleaning of the VOC-free water-soluble flux residues was evaluated. Residues were washed and cleaned using the existing equipment sets without any change in the process parameters. The process developed based on the initial set of experiments has been validated by the successful assembly of a number of lead-free prototype assemblies

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Abstract: Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7/spl times/10/sup -6/ K/sup -1/ (25/spl deg/C-100/spl deg/C) and a thermal conductivity of 147 Wm/sup -1/K/sup -1/ at 30/spl deg/C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100/spl deg/C-400/spl deg/C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30/spl deg/C to 400/spl deg/C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

An Experimental and Numerical Investigation Into Multilayer Probe Card Layout Design

Abstract: This paper conducts experimental and numerical investigations into the microforce probing technique used to test the functionality of IC devices. The study commences by considering the case of a single tungsten needle probe and examines the relationship between the contact force and the scrub mark size on aluminum pads at various levels of overdrive and shooting angle. Subsequently, a three-dimensional computational model is developed to facilitate the design of an optimum multilayer needle card layout. The simulation results obtained for the profile and size of the scrub marks on the upper surface of the aluminum pads of an IC device are found to be in good agreement with the experimental observations. The validated model is then applied to analyze the effects of the tip length and beam length on the scrub mark profile and the stress distribution contours within the needle during a wafer level test. The results predicted by the finite-element model (FEM) for the scrub mark length under various beam lengths are used to specify a suitable design for a multilayer needle layout. Taking the case of DDR2 SDRAM of an aluminum pad of dimensions 70 mumtimes70 mum (length by width), the numerical results enable appropriate values to be assigned to the shooting angles, beam lengths, and tip lengths of the individual needles within a four-layer probe card

Real-Time Quality Evaluation of Wire Bonding Using Input Impedance

Abstract: Input impedance characterizes the dynamic property of a linear system. A few existing technologies thus exploit input electrical impedance of wire bonders as the signature to monitor ultrasonic wire bonding processes. However, the waveforms of "impedance" in these technologies are evaluated only approximately. To overcome the shortcoming, we propose a method to detect the true waveforms of both the real and imaginary part of the input impedance. In the method, the voltage and current at the input port of a wire bonder are probed and processed to obtain impedance via Hilbert Transform. Because dynamics of a bonding process represented by these waveforms is fully responsible for the resulted bonding quality, a quality evaluation system based on pattern recognition of these waveforms is further proposed. An artificial neural network using back propagation as training scheme learns from a set of training data to correlate a few features of the impedance waveforms with the bonding strength of the corresponding bond identified by shearing tests. Through a set of verification data, the built system is validated to be capable of evaluating bonding quality right after a bonding process. The proposed method is not only in situ and real-time, but also sensorless, which means that the system is easy to be implemented without interfering operation

Mechanical Strength and Interface Characteristics of Transmission Laser Bonding

Abstract: A laser-based bonding technique, called transmission laser bonding (TLB), is studied for the purposes of device and wafer-level packaging. The TLB technique uses the specific characteristics of a laser to bond a transparent wafer on top of an opaque wafer. When a laser beam with a specific wavelength is passed through a transparent wafer, high-density laser energy is absorbed by the opaque wafer and melts a thin surface layer, resulting in the formation of strong chemical bonds across the two wafers. A Nd:YAG pulse laser has been used to bond a transparent glass wafer to a Si substrate. The associated bond strengths under various bonding conditions are examined by a microtensile tester to quantify the bonding quality. With a contact pressure higher than 0.5 MPa, the TLB strength can reach a stable value of 10.5 MPa, which is comparable to those obtained by other popular bonding processes currently used by the packaging industry. The wafer surface conditions are evaluated by atomic force microscopy (AFM) and profilometry, while Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) are used to study the characteristics of bonding interfaces. The AFM and profilometry results reveal that the wafer roughness and flatness required by TLB can be less stringent than those specified in the current industrial standards. The AES and XPS results are used to interpret the chemical and physical aspects of TLB formation and to provide the rationale for obtaining high-quality and high-strength TLB

Run-to-run failure detection and diagnosis using neural networks and Dempster-Shafer theory: an application to excimer laser ablation

Abstract: The formation of microvias in multilayer substrates is a critical factor in microelectronic packaging manufacturing. Such microstructures can be produced efficiently by excimer laser ablation. Thus, laser ablation systems are evolving to a level where the need to offset high capital equipment investment and lower equipment downtime are imminent. This paper presents a methodology for inline failure detection and diagnosis of the excimer laser ablation process. The methodology employs response data originating directly from the equipment and characterization of microvias formed by the ablation process. Neural network (NN) models are trained and validated based on this data to generate evidential belief for potential sources of deviations in the responses. Dempster-Shafer (D-S) theory is adopted for evidential reasoning. Successful failure detection is achieved in 100% of 19 possible failure scenarios. Moreover, successful failure diagnosis is also achieved with only a single false alarm occurring in the 19 failure scenarios.

Plastic separation planning for end-of-life electronics

Abstract: Important challenges remain for sustainable design, manufacture, use, and recycling of electronics including materials selection and disassembly time. This paper examines the value relationship between the quantity of plastics separated and the time required for disassembly and segregation. Labor costs for disassembly can constitute a large portion of the total acquisition cost for a recycled material. We report work measurement studies conducted on the disassembly of 21 computers, 22 printers, and 32 monitors manufactured by 27 producers in the years from 1984 to 2001. Results include the weight per total separation time for each plastic part. Each recovered part is identified according to polymer resin using laser Raman spectroscopy by chemometric reference to a library of standards. We extrapolate time as well as the product input required to accumulate various specific types of plastic. We develop disassembly policies and show that they are effective for a variety of computer, printer, or monitor models, which is typical of the random product streams that arrive at electronics recycling facilities. The results demonstrate how new laser identification technology and work measurement can be used for plastics separation planning.

Using Transmission Laser Bonding Technique for Line Bonding in Microsystem Packaging

Abstract: The transmission laser bonding (TLB) technique has been developed for the formation of continuous line bonds for microsystem packaging applications. Line bonds are generated by overlapping single bonding spots, in which the degree of overlapping is achieved by varying the scanning speed of the laser as it irradiates the bonding wafers. An analytical model has been developed to guide the TLB process, attaining a uniform laser intensity that produces uniform bonds, satisfying the bonding requirements. Guided by this model, experiments have been conducted to bond Pyrex glass-to-Si wafers at various bonding conditions. To demonstrate the reliability of the technique and the model developed, the strength of the resulting bonded pairs has been evaluated by a micro tensile tester. At contact pressures higher than 1 MPa, the strength of bonded lines can reach a stable value of 9.2 MPa, which is comparable to those obtained by other major bonding processes. To further understand the associated bonding mechanism, the bonded interface has also been analyzed using auger electron spectroscopy and X-ray photoelectron spectroscopy, quantifying the drifting or diffusion of atoms that occurs between glass and Si wafers during the bonding process

Double bump flip-chip assembly

Abstract: Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.

Copper Direct Drilling With TEA $hbox CO_2$ Laser in Manufacture of High-Density Interconnection Printed Circuit Board

Abstract: A method for copper direct drilling by carbon dioxide (CO2 ) laser was investigated for efficient microvia formation on the copper conducting layer of high-density interconnection (HDI) of printed circuit board (PCB). A metal-tin layer was coated on the surface of copper conductor foil to enhance the CO2 laser energy adsorption on it. The coated surfaces were then drilled by a CO2 laser with various pulse energies. The microvia holes were efficiently formed in good quality with one laser pulse on 9-mum-thick polished copper conducting layer. The laser energy absorption of coated copper foils was approximately calculated. The experimental results demonstrated the potential application of the developed method in high-density interconnection printed circuit board manufacturing