Open AccessProceedings Article
A 1.1 NS Access Time 4 Kb Bipolar RAM Using Super Self-Aligned Technology
H. Miyanaga,Y. Kobayashi,S. Konaka,Y. Yamamoto,Tetsushi Sakai +4 more
- pp 50-51
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This article is published in Symposium on VLSI Technology.The article was published on 1984-09-01 and is currently open access. It has received 11 citations till now. The article focuses on the topics: Read-write memory & Non-volatile random-access memory.read more
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A 30-ps Si bipolar IC using super self-aligned process technology
TL;DR: In this article, a new 30-ps Si bipolar IC was developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions, achieving propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V.
Journal ArticleDOI
A 1.0-ns 5-kbit ECL RAM
TL;DR: In this article, a bipolar 512/spl times/10-bit emitter-coupled logic (ECL) RAM with an access time of 1.0 ns and a power dissipation of 2.4 W, achieving an access-time power/bit product of 0.48 pJ/bit, was developed.
Journal ArticleDOI
A 0.85-ns 1-kbit ECL RAM
TL;DR: A 1-kb ECL RAM with an address access time of 0.85 ns is described, achieving excellent performance by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design.
Journal ArticleDOI
A subnanosecond 5-kbit bipolar ECL RAM
Ching-Te Chuang,D.D. Tang,Guann-Pyng Li,R.L. Franch,M.B. Ketchen,T.H. Ning,K.H. Brown,C.-C. Hu +7 more
TL;DR: In this article, a subnanosecond 512*10b bipolar ECL RAM using a 1.2- mu m silicon-filled trench-isolated double-poly self-aligned bipolar technology in conjunction with a novel sense-amplifier reference circuit configuration is described.
Journal ArticleDOI
Challenges in advanced semiconductor technology in the USLI Era for computer applications
TL;DR: The capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high performance and supercomputer applications and the packaging needs to support advanced chip technologies are reviewed.