Journal ArticleDOI
A class of optimal minimum odd-weight-column SEC-DED codes
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The class of codes described in this paper is used for single-error correction and double-error detection (SEC-DED) and is equivalent to the Hamming SEC-D ED code in the sense that for a specified number of data bits, the same number of check bits r is used.Abstract:
The class of codes described in this paper is used for single-error correction and double-error detection (SEC-DED). It is equivalent to the Hamming SEC-DED code in the sense that for a specified number k of data bits, the same number of check bits r is used. The minimum odd-weight-column code is suitable for applications to computer memories or parallel systems. A computation indicates that this code is better in performance, cost and reliability than are conventional Hamming SEC-DED codes.read more
Citations
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Journal ArticleDOI
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
C. L. Chen,M. Y. Hsiao +1 more
TL;DR: The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided.
Book
The art of error correcting coding
TL;DR: This chapter discusses encoding and decoding of binary BCH codes as well as some of the techniques used in the Viterbi algorithm, which simplifies the decoding process and increases the chances of success in the face of uncertainty.
Book
Architecture Design for Soft Errors
TL;DR: This book provides a comprehensive description of the architetural techniques to tackle the soft error problem, and covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them.
Journal ArticleDOI
On-Line Testing for VLSI—A Compendium of Approaches
TL;DR: An overview of a comprehensive collection of on-line testing techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.
Journal ArticleDOI
Single event upset in avionics
A. Taber,E. Normand +1 more
TL;DR: In this article, error detection and correction circuitry for all avionics designs containing large amounts of semiconductor memory was suggested for all aircraft designs, including SRAMs and NVRAMs, and it was shown that typical nonradiation-hardened 64 K and 256 K static random access memories (SRAMs) experienced a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere.
References
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Journal ArticleDOI
Error detecting and error correcting codes
TL;DR: The author was led to the study given in this paper from a consideration of large scale computing machines in which a large number of operations must be performed without a single error in the end result.