A CMOS Front-End for Timing and Charge Readout of Silicon Photomultipliers

TLDR: In this article, a multichannel application-specific integrated circuit (ASIC) is proposed to read out Silicon Photomultipliers (SiPMs) in a standard CMOS 130 nm technology.

Abstract: The present work describes a new channel architecture suited to reading out Silicon Photomultipliers (SiPM). The aim is to develop a multichannel Application-Specific Integrated Circuit (ASIC) in a standard CMOS 130 nm technology that achieves excellent timing accuracy while fully exploiting the dynamic range of large area SiPMs. The sensor is AC-coupled to the differential front-end, which features two separated timing and charge signal processing paths. The first one exploits a differential input current-mode preamplifier and an embedded Time-to-Digital Converter (TDC) that exhibits a 10 ps binning. Accurate timing and low jitter are also attained by means of a high-speed discriminator with threshold adjustable in small steps just above the baseline, which operates on the very steep edge of the output signal produced by the preamplifier. The charge measurement signal path is based on an active-RC integrator, a peak detector and an Analog-to-Digital Converter (ADC). Operating the front-end at 1.2 V supply voltage, with a power consumption of 10 mW, a simulated Single-Photon Time Resolution (SPTR) of 78 ps at Full-Width Half Maximum (FWHM) is achieved, linearly covering an input dynamic range of 1280 pC that corresponds to ~ 8000 photoelectrons with a SiPM gain of ~ 106.