Journal ArticleDOI
A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits
Masakazu Shimizu,Koki Abe +1 more
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TLDR
A key aspect of this four-phase handshake protocol is that it uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase.Abstract:
We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 μm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.read more
Citations
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Proceedings ArticleDOI
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries
Masashi Imai,Takashi Nanya +1 more
TL;DR: A 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style.
References
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Proceedings ArticleDOI
GasP: a minimal FIFO control
TL;DR: The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, with assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort.
Journal ArticleDOI
Four-phase micropipeline latch control circuits
Steve Furber,P. Day +1 more
TL;DR: An investigation has been carried out into four-phase micropipeline control circuits, which has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.
Proceedings ArticleDOI
MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines
Montek Singh,Steven M. Nowick +1 more
TL;DR: A new asynchronous pipeline design is introduced for high-speed applications that uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per pipeline stage, to handle more complex system architectures.
Proceedings ArticleDOI
Handshake protocols for de-synchronization
TL;DR: This paper studies different protocols for de-synchronization and formally proves their correctness and proposes a new controller with maximum concurrency with respect to micro-pipelines.
Proceedings ArticleDOI
A FIFO ring performance experiment
TL;DR: In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design and from test measurements, it is estimated that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million persecond for the fastest chip.