A novel 2D filter design methodology for heterogeneous devices
Christos-Savvas Bouganis,George A. Constantinides,Peter Y. K. Cheung +2 more
- pp 13-22
Reads0
Chats0
TLDR
An algorithm is proposed that explores the implementation architecture of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device.Abstract:
In many image processing applications, fast convolution of an image with a large 2D filter is required. Field programable gate arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This paper proposes an algorithm that explores the implementation architecture of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device. Experiments show that the proposed algorithm can achieve a reduction in the required area in a range o to 70% when compared to current techniques.read more
Citations
More filters
Journal ArticleDOI
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
TL;DR: A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers, applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence.
Proceedings ArticleDOI
Optimizing Logarithmic Arithmetic on FPGAs
TL;DR: A general polynomial approximation approach with an adaptive divide-in-halves segmentation method for evaluation of LNS arithmetic functions is introduced and a library generator is developed that automatically generates optimized L NS arithmetic units with a wide bit-width range to support LNS application development and design exploration.
Journal ArticleDOI
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
TL;DR: This article proposes an algorithm that explores the space of possible implementation architectures of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device.
Journal ArticleDOI
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
F. Javier Toledo-Moreo,J. Javier Martínez-Álvarez,Javier Garrigós-Guerrero,J. Manuel Ferrández-Vicente +3 more
TL;DR: A hardware architecture for the FPGA-based implementation of 2-D convolution with medium-large kernels is presented, a multiplierless solution based on Distributed Arithmetic implemented using general purpose resources in FPGAs and is modular and coefficient independent.
Journal ArticleDOI
Architectural synthesis of fixed-point DSP datapaths using FPGAs
TL;DR: The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefit of a wise use of embedded FPGA resources.
References
More filters
Numerical recipes in C
TL;DR: The Diskette v 2.06, 3.5''[1.44M] for IBM PC, PS/2 and compatibles [DOS] Reference Record created on 2004-09-07, modified on 2016-08-08.
Book
Introduction to Linear Algebra
TL;DR: The fifth edition of this hugely successful textbook retains the quality of earlier editions while at the same time seeing numerous minor improvements and major additions as mentioned in this paper, including a new chapter on singular values and singular vectors, including ways to analyze a matrix of data.
Book
Computer Arithmetic Algorithms
TL;DR: The principles of the algorithms available for performing arithmetic operations in digital computers, described independently of specific implementation technology and within the same framework, are explained.
BookDOI
Dynamic Vision: From Images to Face Recognition
TL;DR: Many of the issues raised are relevant to object recognition in general, and such visual learning machines have numerous potential applications in areas such as visual surveillance multimedia and visually mediated interaction.
Journal ArticleDOI
Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm
TL;DR: Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.