A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control
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TLDR
This paper presents a new full-chip grid-based routing system considering wire density for reticle planarization enhancement, which applies a novel two-pass top-down planarity-driven routing framework that employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation.Abstract:
As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following time-consuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.read more
Citations
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Journal ArticleDOI
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
TL;DR: This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router and proposes two efficient via-minimization methods.
Proceedings ArticleDOI
Performance-impact limited-area fill synthesis
TL;DR: In this article, the performance impact of area fill insertion is considered and three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method are described.
Proceedings ArticleDOI
Stitch-aware routing for multiple e-beam lithography
TL;DR: Experimental results show that the stitch-aware routing framework can effectively reduce stitching line-induced bad patterns and thus may not only improve the manufacturability but also facilitate the development of MEBL.
References
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Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
TL;DR: A two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations.