Journal ArticleDOI
A spanning tree carry lookahead adder
Reads0
Chats0
TLDR
The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described, which employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees.Abstract:
The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >read more
Citations
More filters
Journal ArticleDOI
Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates
TL;DR: This paper proposes a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones to reduce the threshold-voltage loss of the pass transistors.
DissertationDOI
Binary adder architectures for cell-based VLSI and their synthesis
TL;DR: It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design.
Journal ArticleDOI
High-speed parallel-prefix VLSI Ling adders
TL;DR: Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.
Journal ArticleDOI
Adaptive control of uncertain Chua's circuits
Shuzhi Sam Ge,Chao Wang +1 more
TL;DR: In this article, the adaptive backstepping control of the Chua's circuits with all the parameters unknown is considered, and an adaptive back-stepping with tuning functions method is extended to this non-autonomous "strict-feedback" system, and then employed to control the output of the chua's circuit to asymptotically track an arbitrarily given reference signal generated from a known, bounded and smooth nonlinear reference model.
Journal ArticleDOI
Fast combinatorial RNS processors for DSP applications
TL;DR: It is proven that existing combinatorial or look-up table approaches for RNS are tailored to small designs or special applications, while the pseudo-RNS approach remains competitive also for complex systems.
References
More filters
Journal ArticleDOI
A Regular Layout for Parallel Adders
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI
Conditional-Sum Addition Logic
TL;DR: A comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.
Journal ArticleDOI
Carry-Select Adder
TL;DR: The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design.
Proceedings ArticleDOI
Fast area-efficient VLSI adders
Tackdon Han,David A. Carlson +1 more
TL;DR: A new graph representation for prefix computation is presented that leads to the design of a fast, area-efficient binary adder, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs.
Journal ArticleDOI
High-speed binary adder
TL;DR: A new scheme is presented in which the new carry propagation is examined by including the neighboring pairs (ai, bi; ai+1, bi+1), which not only reduces the component count in design, but also requires fewer logic levels in adder implementation.