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Book ChapterDOI

Amplified differential power cryptanalysis on Rijndael implementations with exponentially fewer power traces

TLDR
It is pointed out that enhanced implementations of the Rijndael cipher (AES) against timing cryptanalysis and simple power crypt analysis (SPA) may unfortunately become more vulnerable to the differential power cryptanalysis (DPA).
Abstract
Recently, many research works have been conducted about how to carry out physical cryptanalysis on cryptographic devices by exploiting any possible leaked information through side channels. Research results were also reported on how to develop countermeasures against existing physical cryptanalysis. However, very little attention has been paid to deal with the possible mutual relationship between different kinds of physical cryptanalysis when designing a specific countermeasure. In this paper, it is pointed out that enhanced implementations of the Rijndael cipher (AES) against timing cryptanalysis and simple power cryptanalysis (SPA) may unfortunately become more vulnerable to the differential power cryptanalysis (DPA). Technically speaking, based on Sommer's work and experiments presented in CHES 2000, this new DPA on the above mentioned Rijndael implementations enables a much more significant observable peak within the differential power trace. This makes the DPA attack be more easier with fewer required power traces.

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Citations
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Book ChapterDOI

Differential fault analysis on AES key schedule and some countermeasures

TL;DR: This paper describes a DFA attack on the AES key schedule that efficiently finds the key of AES-128 with feasible computation and less than thirty pairs of correct and faulty ciphertexts.
Journal ArticleDOI

Effect of glitches against masked AES S-box implementation and countermeasure

TL;DR: Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.
Proceedings ArticleDOI

Preventing the Side-Channel Leakage of Masked AES S-Box

TL;DR: A balanced masked multiplier where the inputs are synchronized either by sequential components or controlled AND logic, that can be a possible solution for preventing DPA attack on masked implementers of AES S-Boxes is proposed.
Book ChapterDOI

Design of a differential power analysis resistant masked AES S-box

TL;DR: A masking technique for AND gates is proposed, which is then used to build a balanced and masked multiplier in GF(2n) and the circuits are shown to be computationally secure and have no glitches which are dependent on unmasked data.
Proceedings ArticleDOI

Anatomy of Differential Power Analysis for AES

TL;DR: This paper describes in detail a step-wise explanation of the differential power analysis of an AES implementation, with all of the aspects identified above.
References
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Book ChapterDOI

Differential Power Analysis

TL;DR: In this paper, the authors examine specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. And they also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.
Book ChapterDOI

Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems

TL;DR: By carefully measuring the amount of time required to perform private key operalions, attackers may be able to find fixed Diffie-Hellman exponents, factor RSA keys, and break other cryptosystems.
Book ChapterDOI

Differential Fault Analysis of Secret Key Cryptosystems

TL;DR: This work states that this attack is applicable only to public key cryptosystems such as RSA, and not to secret key algorithms such as the Data Encryption Standard (DES).