An Over-Cell Gate Array Channel Router
Howard E. Krohn
- pp 665-670
Reads0
Chats0
TLDR
A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density and Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels.Abstract:
A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. Macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. Each loose horizontal channel segment is assigned to a channel track using a maze router. Vertical channel segments are completed by a modified dogleg channel router.read more
Citations
More filters
Book
Algorithms for VLSI Physical Design Automation
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Journal ArticleDOI
Over-the-cell channel routing
Jingsheng Cong,C. L. Liu +1 more
TL;DR: An over-the-cell channel router that produces solutions which are better than the optimal two-layer channel routing solutions for all test examples is designed and outperforms the over- the- cell channel router described by Y. Shiraishi and Y. Sakemi.
Proceedings ArticleDOI
General models and algorithms for over-the-cell routing in standard cell design
TL;DR: This paper presents three physical models to utilize the area over the cells for routing in standard cell designs, and presents efficient algorithms to choose and to route a planar subset of nets over the Cells so that the resulting channel density is reduced as much as possible.
Patent
Interconnection area decision processor
TL;DR: In this article, the authors proposed an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. But, the proposed solution is limited to the case of single-input single-out (SISO) gate arrays.
Journal ArticleDOI
A Permeation Router
Y. Shiraishi,J. Sakemi +1 more
TL;DR: A permeation routing algorithm is proposed which decides the detailed routes on a new layout model and attains a higher density by using the expanded routing region as well as the conventional one simultaneously.
References
More filters
Proceedings ArticleDOI
A “DOGLEG” channel router
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Proceedings ArticleDOI
An Over-The-Cell Router
David N. Deutsch,Paul Glick +1 more
TL;DR: The over-the-cell routing problem is defined, the algorithms for its solution are described, and typical routing results are presented.
Proceedings ArticleDOI
Efficient Placement and Routing Techniques for Master Slice LSI
TL;DR: This paper deals with placement and routing techniques for master slice LSIs to make wiring density on the chip more uniform.
Proceedings ArticleDOI
A Generalized Channel Router
TL;DR: A demonstration of the versatility of the router (it is used to solve the Hampton Court Maze) and with applications of the Router in TI's I2L (Integrated Injector Logic) / STL (Schottky Transistor Logic) Automatic Layout System.
Proceedings ArticleDOI
A "Grid-free" Channel Router
TL;DR: A "grid-free" channel router (termed GFR) is reported that does not employ grid lines and can obtain better results than the fixed-grid method and has several optional functions, such as "constraint loop breaking", "total branch length minimization", "Constraint chain cutting" and "layer changing".