Patent
Apparatus and methods for determining critical area of semiconductor design data
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TLDR
In this paper, a method for determining critical area for a semiconductor design layout is disclosed, where the critical area is used to predict yield of the semiconductor device fabricated from such a design layout.Abstract:
Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.read more
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References
More filters
Patent
Electron beam inspection system and method
Dan Meisburger,Alan D. Brodie,Curt H. Chadwick,Desai Anil,Hans Dohse,Emge Dennis,John D Greene,Ralph H. Johnson,Ling Ming-Yie,Mcmurtry John,Barry Becker,Paul Ray,Michael B. Robinson,Richard R. Simmons,Smith David E A,John C. Taylor,Lee H. Veneklasen,Dean Walters,Wieczorek Paul,Sam Wong,April Dutta,Lele Surendra,Rough Kirkwood,Henry Pearce-Percy,Jau Jack Y,Chun C. Lin,Hoi T. Nguyen,Oyang Yen-Jen,Hutcheson Timothy L,David J. Clark,Chung-Shih Pan,Chetana Bhaskar,Kirk Chris,Eric Munro +33 more
TL;DR: In this article, a substrate is mounted on an x-y stage to provide at least one degree of freedom while the substrate is being scanned by the charged particle beam, and an optical alignment system for initially aligning the substrate beneath the particle beam.
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Method of detecting defects in patterned substrates
TL;DR: In this article, the authors used a large-scale FOV imaging system with a substantially uniform resolution over the FOV to acquire images over a wide area of the patterned substrate without requiring mechanical stage moves.
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System and method for product yield prediction
Brian E. Stine,Christopher Hess,John Kibarian,Kimon Michaels,Joseph C. Davis,Purnendu K. Mozumder,Sherry F. Lee,Larg Weiland,Dennis Ciplickas,David M. Stashower +9 more
TL;DR: In this paper, an extraction engine extracts predetermined layout attributes from a proposed product layout and produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
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Semiconductor and integrated circuit device yield modeling
TL;DR: In this article, the number of defects for each chip, rather than average defect density, is used in the prediction model for an integrated circuit manufacturing process, and an overall predicted yield is obtained from individual yields calculated for regions of approximately homogenous yield within the region.
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Method and apparatus for detecting defects in wafers
TL;DR: In this article, a method for detecting electrical defects in a semiconductor wafer, including the steps of applying charge to the wafer such that electrically isolated structures are raised to a voltage relative to electrically grounded structures, is described.