Journal ArticleDOI
ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling
TLDR
An abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer for MPSoC designers to explore and analyze the network performance under different traffic and load conditions.Abstract:
One of the challenges of designing a heterogeneous multiprocessor SoC is to find the right partitioning of the application for the target platform architecture. The right partitioning is dependent on the characteristics of the processors and the network connecting them as well as the application. We present an abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer. ARTS allows MPSoC designers to explore and analyze the network performance under different traffic and load conditions, consequences of different task mappings to processors (software or hardware) including memory and power usage, and effects of RTOS selection, including scheduling, synchronization and resource allocation policies.
We present the application and platform models of ARTS as well as their implementation in SystemC. We present the usage of the ARTS framework as seen from platform developers' point of view, where new components may be created and integrated into the framework, and from application designers' point of view, where existing components are used to explore possible implementations. The latter is illustrated through a case study of a real-time, smart phone application consisting of 5 applications with a total of 114 tasks mapped onto different platforms. Finally, we discuss the simulation performance of the ARTS framework in relation to scalability.read more
Citations
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Proceedings ArticleDOI
A Fast Emulation-Based NoC Prototyping Framework
TL;DR: An FPGA emulation-based fast network on chip (NoC) prototyping framework, called dynamic reconfigurable NoC (DR noC) emulation platform, which combines the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system.
Proceedings ArticleDOI
A high-level virtual platform for early MPSoC software development
Jianjiang Ceng,Weihua Sheng,Jeronimo Castrillon,Anastasia Stulova,Rainer Leupers,Gerd Ascheid,Heinrich Meyr +6 more
TL;DR: This paper introduces a High-level Virtual Platform (HVP) which aims at early MPSoC software development and shows that the code developed on the HVP can be easily reused on different target platforms and improves the design efficiency of software developers.
Journal ArticleDOI
Models and formal verification of multiprocessor system-on-chips
TL;DR: This article develops a model for applications running on multiprocessor platforms and presents a discrete model of computation for such systems and characterize the size of the computation tree it suffices to consider when checking for schedulability.
Proceedings ArticleDOI
AdapNoC: A fast and flexible FPGA-based NoC simulator
TL;DR: A dual-clock architecture is implemented as an innovation in virtualization methodology, which is also capable to share idle time-slots, which helps not only simulate bigger NoCs, but also reduce simulation time drastically.
Journal ArticleDOI
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture
TL;DR: A two-layer configurable global interconnection is implemented in the proposed architecture to reduce virtualization time overhead, make an efficient trade-off between the resource utilization and simulation time of the whole simulator, and especially provide the capability of simulating irregular topologies.
References
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Journal ArticleDOI
Priority inheritance protocols: an approach to real-time synchronization
TL;DR: An investigation is conducted of two protocols belonging to the priority inheritance protocols class; the two are called the basic priority inheritance protocol and the priority ceiling protocol, both of which solve the uncontrolled priority inversion problem.
Book
System Design with SystemC
TL;DR: System Design and SystemC provides a comprehensive introduction to the powerful modeling capabilities of the SystemC language, and also provides a large and valuable set of system level modeling examples and techniques.
Book
Virtual-channel flow control
TL;DR: Simulation studies show that, given a fixed amount of buffer storage per link, virtual-channel flow control increases throughput by a factor of 3.5, approaching the capacity of the network.
Journal ArticleDOI
Virtual-channel flow control
TL;DR: Simulation studies show that, given a fixed amount of buffer storage per link, virtual-channel flow control increases throughput by a factor of 3.5, approaching the capacity of the network.
Proceedings ArticleDOI
Analyzing on-chip communication in a MPSoC environment
TL;DR: The simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.