Journal ArticleDOI
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics
Reads0
Chats0
TLDR
ASIC design of a high speed low power circuit for factorial calculation of a number and improvements in speed and power consumption were found in comparison with UT and NND based implementations, respectively.About:
This article is published in Microelectronics Journal.The article was published on 2011-12-01. It has received 40 citations till now. The article focuses on the topics: Multiplication & Factorial.read more
Citations
More filters
Proceedings ArticleDOI
High speed vedic multiplier designs-A review
TL;DR: Compressor based Vedic Multipliers based on Vedic mathematics show considerable improvements in speed and area efficiency over the conventional ones.
Journal ArticleDOI
Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic
Mohan Shoba,Rangaswamy Nakkeeran +1 more
TL;DR: A method to reduce the computation delay of hierarchy multiplier by employing CslA and Binary to Excess 1 Converter (BEC) is proposed and it is examined that the proposed multiplier operates with 17% lesser power delay product than the recently reported hierarchy multiplier.
Journal ArticleDOI
A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders
Yogita Bansal,Charu Madhu +1 more
TL;DR: A novel architecture of Vedic multiplier with 'Urdhava-tiryakbhyam' methodology for 16 bit multiplier and multiplicand is proposed with the use of compressor adders and shows good speed results over Traditional multiplier.
Journal ArticleDOI
Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics☆
TL;DR: This work proposes designing of high speed floating point multipliers using Vedic Mathematics, which has a regular structure therefore can be easily layout in a Silicon chip.
Journal ArticleDOI
Time efficient signed Vedic multiplier using redundant binary representation
TL;DR: This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary representation in Urdhva Tiryagbhyam (UT) sutra, the first ever effort towards extension of Vedic algorithms to the signed numbers.
References
More filters
Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI
Signed-Digit Numbe Representations for Fast Parallel Arithmetic
TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Related Papers (5)
Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier
Parth Mehta,Dhanashri H. Gawali +1 more