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Proceedings ArticleDOI

Built in self repair for embedded high density SRAM

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TLDR
A novel methodology that extends the BIST concept to diagnosis and repair utilizing redundant components and allows for the autonomous repair of defective circuitry without external stimulus is described.
Abstract
As the density of embedded memory increases, manufacturing yields of integrated circuits can reach unacceptable limits. Normal memory testing operations require BIST to effectively deal with problems such as limited access and "at speed" testing. In this paper we describe a novel methodology that extends the BIST concept to diagnosis and repair utilizing redundant components. We describe an application using redundant columns and accompanying algorithms. It allows for the autonomous repair of defective circuitry without external stimulus (e.g. laser repair). The method has been implemented with negligible timing penalties and reasonable area overhead.

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Citations
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Proceedings ArticleDOI

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

TL;DR: Two-dimensional (2D) error coding in embedded memories is proposed, a scalable multi-bit error protection technique to improve memory reliability and yield and it is shown that 2D error coding can correct clustered errors up to 32times32 bits with significantly smaller performance, area, and power overheads than conventional techniques.
Journal ArticleDOI

Built-in redundancy analysis for memory yield improvement

TL;DR: Three redundancy analysis algorithms which can be implemented on-chip based on the local-bitmap idea are presented: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate.
Journal ArticleDOI

Embedded-memory test and repair: infrastructure IP for SoC yield

TL;DR: The authors solution integrates memory IP with test and repair IP in a composite infrastructure IP that ensures manufacturing and field repair efficiency and optimizes SoC yield.
Proceedings ArticleDOI

An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264

D.K. Bhavsar
TL;DR: An innovative self-test and self-repair technique that generates and analyzes the required failure bitmap information on the fly during self- test and then automatically repairs and verifies the repaired RAM arrays.
Proceedings ArticleDOI

Memory built-in self-repair using redundant words

TL;DR: A word oriented memory Built-In Self-Repair (BISR) methodology is described without modifying the memory module to store Faulty addresses and data immediately after its detection during test.
References
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Book

Testing Semiconductor Memories: Theory and Practice

TL;DR: Memory modeling functional testing: reduced functional RAM chip model Functional RAM chip testing functional ROM chip testingfunctional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
Journal ArticleDOI

Efficient Spare Allocation for Reconfigurable Arrays

TL;DR: Two algorithms for spare allocation that are based on graph-theoretic analysis are presented, which provide highly efficient and flexible reconfiguration analysis and are shown to be NP-complete.
Journal ArticleDOI

Built-in self-diagnosis for repairable embedded RAMs

TL;DR: A method of built-in self-diagnosis (BISD) for repairable, embedded static RAMs (SRAMs) is presented and the algorithms, hardware design, and design costs and tradeoffs are discussed.
Journal ArticleDOI

Increased throughput for the testing and repair of RAMs with redundancy

TL;DR: The problem of determining whether a redundant random-access memory (RRAM) containing faulty memory cells can be repaired with spare rows and columns is discussed and a computationally efficient algorithm for detecting unrepairability is presented.