Proceedings ArticleDOI
Compact Designs of SubBytes and MixColumn for AES
C. Nalini,P.V. Anandmohan,D. V Poomaiah,V.D. Kulkarni +3 more
- pp 1241-1247
TLDR
The proposed work employs a memory-less combinatorial design for the implementation of SB/ISR as an alternative to achieve higher speeds by eliminating memory access delays while retaining or enhancing the over all area efficiency.Abstract:
The most critical factors responsible for bottleneck in the design and implementation of high-speed AES (Advanced Encryption Standard) architectures for any resource constrained target platform such as an FPGA are Substitute byte/Inverse SubstituteByte and MixColumn/InverseMixcolumn operations. Most implementations conventionally make use of the memory intensive look up table approach for Substitute byte/Inverse SubstituteByte (SB/ISR) block implementations resulting in an unbreakable delay. The proposed work employs a memory-less combinatorial design for the implementation of SB/ISR as an alternative to achieve higher speeds by eliminating memory access delays while retaining or enhancing the over all area efficiency. The work also explores use of sub-pipelining to further enhance the speed and throughput of the suggested implementation. The architecture employs optimization in both inverter design and isomorphic mapping using composite field arithmetic to reduce the area requirements. The proposed design replicates the very compact SB/ISR reported in [6] and [13] with an overall reduction in area requirement of 18% and 14% resply. The Optimum construction of composite field for AES S-Box are selected based on the complexities of subfield operations in the design of inverter in GF (28) for the effects of irreducible polynomial coefficients, and isomorphic mappings to minimize gate count and critical path. This decreased size of SB/ISR design could help for an area limited hardware implementations and also to allow more copies of SB/ISR for parallelism and/or pipelining of AES. The proposed decomposition method for integrated MixColumn/InverseMixcolumn (MC/IMC) optimizes the area and path delay.read more
Citations
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Proceedings ArticleDOI
Design of AES S-box using combinational logic optimization
TL;DR: The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip that employs a Boolean simplification of the truth table of the logic function with the aim of reducing the delay.
Journal ArticleDOI
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Nabihah Ahmad,S. M. Rezaul Hasan +1 more
TL;DR: This paper presents a full custom CMOS design of S-Box/Inversion S- Box (Inv S- box) with low power GF (2^8) Galois Field inversions based on polynomial basis, using composite field arithmetic.
Design and implementation of advanced encryption algorithm with fpga and asic
Iyli Sagar,U Eranna +1 more
TL;DR: Development of physical design of AES-128 bit is done using cadence SoC encounter, and performance evaluation of the physical design with respect to area, power, and time has been done.
Design and Implementation of Advanced Encryption Algorithm with FPGA and ASIC
TL;DR: In this article, the AES Rijndael algorithm was implemented on FPGA using Verilog and synthesis using Xilinx, plain text of 128 bit data is considered for encryption using Rijnda algorithm utilizing key.
Journal ArticleDOI
Efficient integrated AES crypto-processor architecture for 8-bit stream cipher
Nabihah Ahmad,S. M. Rezaul Hasan +1 more
TL;DR: Compared to other 8-bit implementations, the proposed design achieves a smaller chip size along with higher throughput and lower power dissipation.
References
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Book ChapterDOI
A Compact Rijndael Hardware Architecture with S-Box Optimization
TL;DR: Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described, including a new composite field and the S-Box structure is also optimized.
Journal ArticleDOI
High-speed VLSI architectures for the AES algorithm
Xinmiao Zhang,Keshab K. Parhi +1 more
TL;DR: Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.
Book ChapterDOI
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
TL;DR: This work explores the use of subfield arithmetic for efficient implementations of Galois Field arithmetic especially in the context of the Rijndael block cipher and describes how to select a representation which minimizes the computation cost of the relevant arithmetic.
Proceedings ArticleDOI
A 21.54 Gbits/s fully pipelined AES processor on FPGA
A. Hodjat,Ingrid Verbauwhede +1 more
TL;DR: This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA by using loop unrolling and inner-round and outer-round pipelining techniques, and achieves a maximum throughput of 21.54 Gbits/s.
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.
Kris Gaj,Pawel Chodowiec +1 more
TL;DR: The results of implementations of all five AES finalists using Xilinx Field Programmable Gate Arrays are presented and analyzed and recommendation regarding the optimum choice of the algorithms for AES is provided.