Open Access
"Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems," pp. 61-69, Proc. IEEE/ACM 28th Design Automation Conf.
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The article was published on 1991-01-01 and is currently open access. It has received 53 citations till now. The article focuses on the topics: Routing (electronic design automation) & Electronic design automation.read more
Citations
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Patent
Method and apparatus for routing
TL;DR: In this paper, the shape of interconnect-line ends is dynamically defined on a particular layer based on the routing directions available on the particular layer to improve the alignment of route segments that have differing widths.
Patent
Routing method and apparatus
TL;DR: In this paper, the authors proposed a routing method that uses diagonal routes to route several nets within a region of a circuit layout, each net includes a set of pins in the region, and then identifies a route that connects the sub-regions that contain a pin from the set of nets of the particular net.
Patent
Method and apparatus for placing circuit modules
Steven Teig,Joseph L. Ganley +1 more
TL;DR: In this paper, the authors propose to use diagonal lines to calculate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout and derive the delay from an estimate of the wirelength needed to route the nets in the region.
Patent
Method and apparatus for routing with independent goals on different layers
Jonathan Frankle,Andrew Caldwell +1 more
TL;DR: In this paper, the authors proposed a routing method for multi-layer networks based on different congestion goals on different layers and between different layer pairs, where the goal is to select a net with a set of routable elements in a multilayer layout region.
Patent
Method and apparatus for considering diagonal wiring in placement
Steven Teig,Joseph L. Ganley +1 more
TL;DR: In this article, the authors use diagonal lines to measure congestion costs of potential placement configurations and estimate the wirelength cost of a placement configuration by using a line that is completely or partially diagonal.
References
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Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Journal ArticleDOI
Hierarchical Wire Routing
M. Burstein,Richard Pelavin +1 more
TL;DR: A new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels and is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
Proceedings ArticleDOI
The constrained via minimization problem for PCB and VLSI design
Xiao-Ming Xiong,Ernest S. Kuh +1 more
TL;DR: A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips and poses a practical heuristic algorithm that can handle both grid-based and gridless routing.
Journal ArticleDOI
Efficient Algorithms for Layer Assignment Problem
K.C. Chang,David H. C. Du +1 more
TL;DR: The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets and an efficient algorithm for identifying essential vias is presented and discussed in this paper.