Journal ArticleDOI
Delay-insensitive gate-level pipelining
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TLDR
Gate-level pipelining techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL), yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.About:
This article is published in Integration.The article was published on 2001-10-01. It has received 76 citations till now. The article focuses on the topics: Asynchronous circuit & Combinational logic.read more
Citations
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Journal ArticleDOI
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
TL;DR: This book focuses on delay-insensitive asynchronous logic design using the NCL paradigm, and details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback.
Journal ArticleDOI
Optimization of NULL convention self-timed circuits
TL;DR: Self-timed logic design methods developed using Threshold Combinational Reduction within the NULL Convention Logic paradigm demonstrate support for a variety of optimizations utilizing conventional Boolean minimization followed by table-driven gate substitutions, providing for an NCL design method that is readily automatable.
Proceedings ArticleDOI
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
TL;DR: This paper employs partial acknowledgement concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method, and results show the average reduction in area and in the number of inter-functional module wires that require timing verification by 67%, compared to NCL-X.
Proceedings ArticleDOI
CMOS implementation of static threshold gates with hysteresis: A new approach
Farhad A. Parsan,Scott C. Smith +1 more
TL;DR: A new approach to design static threshold gates with hysteresis is developed, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network, which shows that the new gate style offers 27% speed-up with only a 5% increase in area and almost the same energy consumption.
Journal ArticleDOI
Design and characterization of null convention self-timed multipliers
TL;DR: This study serves as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.
References
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Journal ArticleDOI
Compiling Communicating Processes into Delay-Insensitive VLSI Circuits
TL;DR: The circuits obtained are delay-insensitive, i.e., their correct operation is independent of any assumption on delays in operators and wires, except that the delays are finite.
Proceedings ArticleDOI
NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis
Karl M. Fant,Scott A. Brandt +1 more
TL;DR: This work introduces NULL Convention Logic in relation to Boolean logic as a four value logic, and as a three value logic and finally as two value logic quite different from traditional Boolean logic.
Journal ArticleDOI
Delay-insensitive codes : an overview
TL;DR: In this paper, the problem of delay-insensitive data communication is described, and the notion of delayinsensitive code is defined, giving precise conditions under which it is possible to use delay-sensitive data communication.
Journal ArticleDOI
Four-phase micropipeline latch control circuits
Steve Furber,P. Day +1 more
TL;DR: An investigation has been carried out into four-phase micropipeline control circuits, which has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.