Design and Analysis of Majority Logic Based Approximate Adders and
Multipliers
Liu, W., Zhang, T., McLarnon, E., O'Neill, M., Montuschi, P., & Lombardi, F. (2019). Design and Analysis of
Majority Logic Based Approximate Adders and Multipliers.
IEEE Transactions on Emerging Topics in Computing
(TETC)
. https://doi.org/10.1109/TETC.2019.2929100
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1
Design and Analysis of Majority Logic Based
Approximate Adders and Multipliers
Weiqiang Liu, Senior Member, IEEE, Tingting Zhang, Emma McLarnon,
Maire O’Neill, Senior Member, IEEE, Paolo Montuschi, Fellow, IEEE and Fabrizio Lombardi, Fellow, IEEE
Abstract—As a new paradigm for nanoscale technologies, approximate computing deals with error tolerance in the computational
process to improve performance and reduce power consumption. Majority logic (ML) is applicable to many emerging nanotechnologies;
its basic building block (the 3-input majority voter, MV) has been extensively used for digital circuit design. In this paper, designs
of approximate adders and multipliers based on ML are proposed; the proposed multipliers utilize approximate compressors and a
reduction circuitry with so-called complement bits. An influence factor is defined and analyzed to assess the importance of different
complement bits depending on the size of the multiplier; a scheme for selection of the complement bits is also presented. The proposed
designs are evaluated using hardware metrics (such delay and gate complexity) as well as error metrics. Compared with other ML-based
designs found in the technical literature, the proposed designs are found to offer superior performance. Case studies of error-resilient
applications are also presented to show the validity of the proposed designs.
Index Terms—majority logic, approximate adder, approximate multiplier, complement bits, approximate compressor, image
processing.
F
1 INTRODUCTION
A
S one of the main obstacles to attain high performance,
power dissipation is increasingly been investigated for
IC design. Approximate computing is a promising tech-
nique to reduce power consumption and improve perfor-
mance of circuits and systems by introducing computa-
tional errors for error-tolerant applications, such as mul-
timedia signal processing, machine learning and pattern
recognition[1-2].
Approximate computer arithmetic circuits based on C-
MOS technology have been extensively studied. Designs of
approximate adders, multipliers and dividers for both fixed-
point and floating-point formats have been proposed [3-6].
Error metrics such as the mean error distance (MED), the
normalized MED (NMED) and the relative MED (RMED)
[7] have been proposed to analyze the errors introduced in
the operations of approximate arithmetic circuits.
As CMOS is approaching its technology limitations, e-
merging nanotechnologies have been proposed at the end
of the so-called Moore’s Law, such as Quantum-dot Cellular
Automata (QCA) [8-9], nanomagnetic logic (NML) [10], and
spin-wave devices (SWD) [11]. All of these technologies rely
on majority logic (ML) as digital design framework; this is
different from conventional Boolean logic. The majority gate
• W. Liu and T. Zhang are with College of Electronic and Information En-
gineering, Nanjing University of Aeronautics and Astronautics, Nanjing,
211106, China. E-mail: {liuweiqiang, ztt0416}@nuaa.edu.cn
• E. McLarnon and M. O’Neill are with the Institute of Electronic-
s, Information and Communication Technologies, Queen’s Universi-
ty Belfast, Belfast, BT3 9DT, UK. E-mail: emclarnon06@qub.ac.uk,
m.oneill@ecit.qub.ac.uk
• P. Montuschi is with the Department of Control and Computer En-
gineering, Politecnico di Torino, Turin, 10129, Italy. E-mail: pao-
lo.montuschi@polito.it
• F. Lombardi is with the Department of Electrical and Computer En-
gineering, Northeastern University, Boston, MA 02115, USA. E-mail:
lombardi@ece.neu.edu
performs a multi-input logic operation (Fig. 1); the logic
expression of the 3-input majority gate (voter, MV) is given
by:
F = M(A, B, C) = AB + BC + AC (1)
M
A
B
C
F
Fig. 1. Majority gate (3-input voter).
It is expected that significant improvement in power
consumption could be achieved by applying approximate
computing also to emerging nanotechnologies. However,
approximate designs of CMOS circuits cannot be directly
applied due to the underlying different logic; few designs
of ML based approximate circuits have been studied [12-15].
[12] has proposed a 1-bit approximate full adder (AFA), but
no multi-bit designs suitable for practical applications have
been outlined. Several ML-based AFAs have been proposed
in [13]; 1-bit as well as multi-bit AFAs are considered. For
an approximate multiplier (AM), [14] has proposed a 4:2 ap-
proximate compressor based on truth table manipulation for
designing an approximate multiplier for image processing.
[15] has proposed two 4:2 approximate compressors based
on the 1-bit AFA of [12].
In this paper, both ML-based AFAs (MLAFAs), and ML-
based AMs (MLAMs) are designed. For the MLAFA, multi-
bit MLAFAs are designed by combining 1-bit MLAFAs.
Moreover, a 2-bit MLAFA with a higher accuracy is de-
signed based on logic reduction. For the MLAM, a 2 × 2
design with complement bits is proposed. Furthermore,
complement bit selection is analyzed as function of the
2
size of a multiplier; a so-called influence factor is intro-
duced to assess the importance of different complement
bits. Few ML-based approximate compressors (MLACs) are
designed by MLAFAs or K-Map simplification; then they
are employed in the reduction circuitry. Error analysis and a
hardware evaluation are presented to validate the proposed
designs. Case studies with the proposed approximate adder-
s and multipliers for image processing are also provided as
part of this assessment.
This paper has been extended significantly from its
previous conference version [13]. The main differences are
summarized as follows:
(1) A new 2-bit MLAFA is proposed based on truth table
reduction; it can be used for multi-bit approximate adder
design;
(2) A 2 × 2 MLAM is proposed and complement bits are
introduced;
(3) A novel analysis for selecting complement bits is
presented;
(4) MLACs based on K-Map simplification and 1-bit
MLAFAs are proposed;
(5) Exact as well as approximate pipelined reduction
circuits for 4 × 4 and 8 × 8 MLAMs are proposed;
(6) Case studies are provided for image processing as
application using the proposed MLAFAs and MLAMs.
The paper is organized as follows: Section 2 reviews re-
lated works and error metrics. Designs of ML based approx-
imate full adders are presented in Section 3 (together with
evaluation and application). Section 4 presents the design
of approximate multipliers by introducing complement bits
and approximate compression which utilizes approximate
compressors and approximate adders. The application of
the proposed approximate multipliers to image processing
and comparison with previous designs are also presented in
Section 4. Section 5 concludes this paper.
2 RELATED WORKS
2.1 ML-based Approximate Designs
2.1.1 ML-based Approximate Full Adder
A 1-bit MLAFA (MLAFA1) has been proposed in [12] (Fig.
2). The inputs are given by A, B, C while S and C
out
are the outputs. MLAFA1 generates the output S as the
complement of C
out
; it introduces 2 errors (among the 8
input combinations) when computing the output S (Table
1), but saving two majority gates and one inverter. The
circled entries in the truth table denote the instances in
which the outputs of MLAFA differ from the exact full adder
(EFA). The equations for the carry out and the sum are as
follows:
C
out
= M (A, B, C) (2)
S = C
out
(3)
2.1.2 ML-based Approximate 4:2 Compressor
As part of a multiplier, a compressor plays an important
role. Let the inputs be P
5
, P
4
, P
3
, P
2
, P
1
and the outputs be
Sum, C
out
, Carry; the implementation of a 4:2 compressor
consists of two serially connected 1-bit full adders[16].
M
A
BC
S
Fig. 2. The schematic diagram of MLAFA1[12].
Using a truth table, [14] has proposed an approximate
4:2 compressor (MLAC1) (Fig. 3(a)). In MLAC1, the Carry
output has the same logic with the input P
5
in 24 out of 32
cases, and similarly, C
out
has the same value as P
4
in 24 out
of 32 cases. So Sum output is modified to reduce the error.
The equations for the outputs are as follows:
C
out
= P
4
(4)
Car ry = P
5
(5)
Sum = M (P
2
, P
3
, M(P
4
, P
5
, P
1
)) (6)
M
M
P
1
P
5
P
4
P
3
P
2
C
out
Carry
Sum
M
M
P
1
P
2
P
3
P
4
P
5
C
out
Carry
Sum
M
M
M
P
1
P
2
P
3
P
4
P
5
C
out
Carry
Sum
(a) (b) (c)
Fig. 3. Schematic diagrams of 4:2 MLACs: (a) MLAC1 [14], (b) MLAC2
[15] (two 1-bit MLAFAs), and (c) MLAC3 [15] (one 1-bit MLAFA and one
1-bit EFA).
[15] has proposed two MLACs (Fig. 3(b) and Fig. 3(c)).
Fig. 3(b) employs two 1-bit MLAFA1s [12] to substitute the
two 1-bit EFAs, so resulting in 12 errors out of 32 cases; to
improve the accuracy, the 1-bit MLAFA1 replaces one of the
two EFAs in MLAC3. MLAC3 requires a 5-input majority
gate; the proposed designs are all based on 3-input majority
gates, therefore MLAC3 is not considered for comparison in
the paper.
2.1.3 Error Metrics
As approximate computing introduces errors, metrics are
required to evaluate the accuracy of approximate circuits.
In this paper, we evaluate approximate designs by the
Normalized Mean Error Distance (NMED), and the Maxi-
mum Absolute Error (MAE). The NMED is the normalizing
Mean Error Distance. The Mean Error Distance (MED) is
defined as the average of the Error Distance (ED) which
is the absolute difference between the approximate and the
accurate results across all possible inputs. MAE is defined as
the maximum absolute error. The definitions of ED, MED,
NMED, and MAE are as follows:
ED = |(ExR − ApR)| (7)
3
MED =
P
ED
N
(8)
NMED =
MED
MAX
(9)
MAE = max{ED} (10)
where ExR, ApR, N and M AX denote the accurate
result, the approximate result, the counts of all possible
inputs and the maximum value of the result, respectively.
3 ML BASED APPROXIMATE FULL ADDER
In this section, a new 1-bit MLAFA (MLAFA2) is proposed;
it is also compared with the 1-bit EFA and the previous 1-
bit MLAFA1 of [12]. Moreover, 2-bit MLAFAs are proposed
by utilizing two methods: the first method merges the pro-
posed and the previous 1-bit MLAFAs; the second method is
based on a truth table reduction process for the 2-bit design.
Multi-bit MLAFAs are also designed by cascading the pro-
posed designs. Both designs and corresponding errors are
evaluated and assessed. A case study for image processing
is also provided.
3.1 Proposed 1-bit MLAFA
A new 1-bit MLAFA, namely MLAFA2 is proposed (Fig. 4).
Consider Table 1, C
out
is nearly the same as C except two
cases out of the 8 input cases. Therefore, in Eq. (11), C can
be approximately made equal to C
out
.
C
out
= C (11)
The approximate output C
out
can be substituted into the
exact expression of S to obtain the approximate S as follows:
S = M (C
out
, M(A, B, C), C) = M (A, B, C) (12)
TABLE 1
Truth Table of 1-bit MLAFAs
Inputs EFA MLAFA1[12] MLAFA2
A B C C
out
S C
out
S C
out
S
0 0 0 0 0 0
1
0 0
0 0 1 0 1 0 1
1
0
0 1 0 0 1 0 1 0 1
0 1 1 1 0 1 0 1 0
1 0 0 0 1 0 1 0 1
1 0 1 1 0 1 0 1 0
1 1 0 1 0 1 0
0
1
1 1 1 1 1 1
0
1 1
The MED and NMED of MLAFA2 are given by:
MED
MLAF A2
=
1
8
(0+1+0+0+0+0+1+0) = 0.25 (13)
NMED
MLAF A2
=
MED
MLAF A2
3
= 0.083 (14)
A comparison in terms of number of majority gates
(MV), number of inverters (INV), NMED, MAE, delay (D)
and delay of carry (D
carry
) between EFA, MLAFA1 [12]
and the proposed MLAFA2 is reported in Table 2. When
considering ML based nanotechnologies, delay (as assessed
in this paper) is normalized by the number of majority
gates only (so, the delay for the inverters is not included
M
A
BC
S
Fig. 4. The schematic diagram of proposed MLAFA2.
because it is often very small compared to the ML gate)
[17]. Compared with EFA, MLAFA2 saves two majority
gates, one inverter and one delay. MLAFA2 decreases the
delay of carry to 0, compared with MLAFA1 [12], which can
reduce the length of the critical path for large scale designs.
Although the proposed MLAFA2 incurs a large error for
Cout (which could be propagated to the higher bits), the
combination of MLAFA1[12] and MLAFA2 introduce fewer
errors than only cascading MLAFA1[12]. This is verified
next.
TABLE 2
Comparison of 1-bit MLAFAs
Types of 1-bit Adders MV INV D D
carry
NMED MAE
EFA 3 2 2 1 0 0
MLAFA1[12] 1 1 1 1 0.083 1
MLAFA2 1 1 1 0 0.083 1
3.2 Proposed 2-bit MLAFAs
In this section, 2-bit MLAFAs are proposed by using two
methods. The first designs merge the proposed MLAFA2
and MLAFA1 (hence the hybrid nature); the second method
designs the 2-bit MLAFA using a truth table reduction
process. The inputs to the 2-bit adder are given by A = a
1
a
0
,
B = b
1
b
0
, C
in
, while S = s
1
s
0
, and C
2
are the outputs.
3.2.1 Hybrid 2-bit MLAFA based on MLAFA2
By cascading two 1-bit MLAFAs (MLAFA1 and MLAFA2),
four different combinations are considered for the 2-bit
MLAFAs; they are shown in Fig. 5(a)-(d). MLAFA1 cas-
caded with MLAFA1 results in the 2-bit MLAFA11 design.
Similarly, MLAFA2 cascaded with MLAFA2 results in the
MLAFA22 design. MLAFA12 consists of MLAFA1 and M-
LAFA2, in which MLAFA1 is used to compute the least
significant bits (LSBs); in MLAFA21, MLAFA2 is used to
compute the LSBs.
M
M
a
1
b
1
a
0
b
0
C
in
C
2
s
0
s
1
MM
a
1
b
1
a
0
b
0
C
in
C
2
s
0
s
1
M
M
a
1
b
1
a
0
b
0
C
in
C
2
s
0
s
1
M
M
a
1
b
1
a
0
b
0
C
in
C
2
s
0
s
1
M
M
M
M
a
1
b
1
a
0
b
0
C
in
C
2
s
0
s
1
(a) (b) (c) (d) (e)
Fig. 5. Schematic diagrams of proposed 2-bit MLAFAs: (a) MLAFA11,
(b) MLAFA22, (c) MLAFA12, (d) MLAFA21, and (e) MLAFA33.
4
3.2.2 2-bit MLAFA from Truth Table Reduction
For two operands A and B, there are four possible combi-
nations. Under an assumed Gaussian distribution for image
processing, A = 00 or B = 00 and A = 11 or B = 11 are
not considered to ensure a low complexity by using a truth
table. The reduced truth table is shown in Table 3. The exact
expressions for the outputs in these eight cases are given
in Eqs. (15)-(17); the schematic diagram is illustrated in Fig.
5(e), this design is hereafter referred to as MLAFA33.
C
2
= M (A
1
, B
1
, C
in
) (15)
s
0
= M (M(A
0
, B
0
, C
in
), M(A
0
, B
0
, C
in
), C
in
)
= M (M(A
1
, B
0
, C
in
), M(A
0
, B
1
, C
in
), C
in
)
(16)
s
1
= C
2
(17)
TABLE 3
Reduced Truth Table of 2-bit MLAFA
Inputs MLAFA33
A B
C
in
C
2
S
a
1
a
0
b
1
b
0
s
1
s
0
0 1 1 0 0 0 1 1
0 1 1 0 1 1 0 0
0 1 0 1 0 0 1 0
0 1 0 1 1 0 1 1
1 0 1 0 0 1 0 0
1 0 1 0 1 1 0 1
1 0 0 1 0 0 1 1
1 0 0 1 1 1 0 0
3.2.3 Comparison and Discussion
The proposed 2-bit approximate hybrid adders based on
MLAFA1 and MLAFA2 introduce errors for 14 of the 32
input cases; the design based on truth table reduction gen-
erates errors for 16 of the 32 input cases. The MAE and
NMED of these MLAFAs are provided in Table 4. MLAFA22
shows the best performance in delay; the errors due to
the inverters have more significance in a multi-bit design.
Moreover, hybrid MLAFAs designed by cascading two of
the same type of 1-bit MLAFAs have larger errors than
cascading two different types of 1-bit MLAFAs. Consider
the number of required gates, MLAFA12 requires one less
inverter than MLAFA21; in terms of delay, MLAFA21 incurs
in 1 less delay than MLAFA12.
For MLAFA33, two additional majority gates are needed
than other 2-bit MLAFAs; however, the NMED is decreased
by 10% compared with MLAFA12 and MLAFA21.
TABLE 4
Comparison of 2-bit MLAFAs
Types of 2-bit Adders MV INV D MAE NMED
MLAFA11 2 2 2 3 0.107
MLAFA22 2 1 1 3 0.107
MLAFA12 2 1 2 2 0.089
MLAFA21 2 2 1 2 0.089
MLAFA33 4 2 2 2 0.080
3.3 Proposed Multi-bit MLAFAs
In this section, multi-bit MLAFAs are considered (including
4-bit and 8-bit designs) by cascading 2-bit MLAFAs.
3.3.1 Proposed 4-bit MLAFAs
Consider a 4-bit MLAFA with inputs given by A =
a
3
a
2
a
1
a
0
, B = b
3
b
2
b
1
b
0
, C
in
and outputs given by S =
s
3
s
2
s
1
s
0
, C
4
. Similar to the proposed hybrid 2-bit MLAFAs,
4-bit MLAFAs can be designed by cascading two 2-bit
MLAFAs (MLAFA12 and MLAFA21).
Table 5 shows that the proposed designs require fewer
gates than an EFA, but at the cost of a reduced accura-
cy. An improvement of up to 50% in delay is achieved.
Although MLAFA1221 has advantages in terms of the
reduced number of gates and delay, its MED/NMED is
the largest. MLAFA2121 and MLAFA2112 have the same
MED/NMED, but MLAFA2121 has less delay. Compared
with MLAFA2112, MLAFA1212 requires one less inverter
with a reduction in MED. Therefore, MLAFA2121 is the best
design which contributes to a reduction of 67% in majority
gates and delay. Moreover, the schemes in which two of
the same type of the proposed 2-bit MLAFAs are cascaded
have better performance than cascading different types of
MLAFAs.
MLAFA33 is employed to control the introduced error
into the most significant bits (MSBs), as shown in Fig. ??(e)-
(f). From Table 5, the designs using MLAFA33 decrease
the NMED below 0.084 at a small hardware utilization.
Improvements of up to 50% in delay and majority gates can
be achieved compared with the exact counterparts.
TABLE 5
Comparison of 4-bit MLAFAs
Types of 4-bit Adders MV INV D MAE NMED
CFA4[18] 12 8 6 0 0
RCA4[19] 12 4 7 0 0
MLAFA1212 4 2 3 10 0.091
MLAFA2121 4 3 2 10 0.092
MLAFA2112 4 3 3 10 0.092
MLAFA1221 4 2 2 10 0.175
MLAFA1233 6 2 3 9 0.083
MLAFA2133 6 3 3 10 0.081
3.3.2 Proposed 8-bit MLAFAs
Consider an 8-bit MLAFA with inputs A =
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
, B = b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
, C
in
and outputs
S = s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
, C
8
. 8-bit MLAFAs are designed by
cascading two 4-bit MLAFAs by using MLAFA1212 and
MLAFA2121.
The comparison results are presented in Table 6. The
proposed designs significantly reduce the number of gates
and delay but at a decrease in accuracy. In terms of
gates, MLAFA1212-1212 and MLAFA1212-2121 require one
less inverter than the other adders; MLAFA2121-2121 and
MLAFA1212-2121 incur in a smaller delay than the other
adders. Compared with MLAFA2121-2121, MLAFA1212-
1212 is superior; the design is also better than the other two
designs, resulting in an improvement of 67% in majority
gates and 50% in delay. So the designs whose LSBs are
processed by MLAFA1212 show considerable advantages.
