Book ChapterDOI
Design and Verification of AMBA AXI3 Protocol
Shweta Sharma,S. M. Sakthivel +1 more
- pp 247-259
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TLDR
High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation.Abstract:
Objective: In this paper, the design and verification of AMBA AXI3 protocol are carried out in a coverage mode analysis using Verilog HDL language. Method: The design of AXI protocol is made according to its architecture specifications, and its functionality is verified using QuestaSim tool. In the AXI protocol analysis, the burst-based transactions, i.e. writing and reading of increment burst have been implemented. Findings: In addition to that the AMBA AXI efficiency is evaluated by calculating performance metrics bus utilization, busy count and valid count. In the entire paper, a verification environment is created for the verification of AXI protocol as a verification IP for modern SOC architectures. Applications: High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation.read more
References
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Proceedings ArticleDOI
A synthesizable AXI protocol checker for SoC integration
TL;DR: This work proposes a rule-based synthesizable AMBA AXI protocol checker, which contains 44 rules to check on-chip communication properties accuracy and uses the Synopsys VIP (Verification IP) to verify AXI Protocol checker.
Proceedings ArticleDOI
Verification of memory transactions in AXI protocol using system verilog approach
Golla Mahesh,S. M. Sakthivel +1 more
TL;DR: Verifying the memory transactions of AXI includes the verification of all the five channels write address, write data, write response, read address and read data and the System connectivity during write and read cycles is one of the fundamental features verified.
Proceedings ArticleDOI
Improving the System-on-a-Chip Performance for Mobile Systems by Using Efficient Bus Interface
Na Ra Yang,Gilsang Yoon,Jeonghwan Lee,Intae Hwang,Cheol Hong Kim,Sung Woo Chung,Jong-Myon Kim +6 more
TL;DR: The proposed EBI is designed to reduce the memory access time by using double buffering, open row access, and bank interleaving and improves the performance of the target system by up to 49%.
Verification IP for an AMBA-AXI Protocol using System Verilog
TL;DR: A coverage driven verification methodology to verify the AMBA AXI Bus protocol with its verification environment is proposed and the whole verification process is carried out using the system verilog based modeling approach.
Proceedings ArticleDOI
Bug analysis and corresponding error models in real designs
TL;DR: The test generation method for item-missing error model, which stems from the analysis of real bugs that are collected in two market-oriented projects, is proposed and results demonstrate the effectiveness of this method.