Journal ArticleDOI
Design for Testability for Complete Test Coverage
Akira Motohara,Hideo Fujiwara +1 more
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TLDR
Two methods aimed at achieving total coverage are presented: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation, and the other employs a test patterngeneration algorithm (the FAN algorithm) that enables us to generate a test patterns for any detectable fault within the allowed time limits.Abstract:
Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.read more
Citations
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Proceedings ArticleDOI
Low overhead test point insertion for scan-based BIST
TL;DR: Efficient test point selection algorithms, which are suitable for utilizing overhead reduction approaches such as restricted cell replacement, test point flip-flops sharing, are proposed to meet the above requirements.
Journal ArticleDOI
Nonscan design for testability for synchronous sequential circuits based on conflict resolution
Dong Xiang,Yi Xu,Hideo Fujiwara +2 more
TL;DR: The nonscan design for testability method based on the conflict measure can reduce many potential backtracks and make many hard-to-detect faults easy todetect; therefore, it can enhance actual testability of the circuit greatly.
Patent
Semiconductor integrated circuit and its analyzing method
Michinobu Nakao,Ryo Yamagata,Kazumi Hatayama,Seiji Kobayashi,Kazunori Hikone,Kotaro Shimamura +5 more
TL;DR: In this article, a semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period, where the plurality of observation points are divided into a preset number of groups.
Patent
Device and method for the generation of test vectors and testing method for integrated circuits
Bernard Dias,Arnaud du Chene +1 more
TL;DR: In this article, a device and a method are used to test integrated circuits, especially P.L.A.s, and a set of test vectors are determined, each fault modifying at least one of the test vectors applied to the circuit to be tested.
Digital Systems Validation Handbook, Volume 3. Design, Test, and Certification Issues for Complex Integrated Circuits - Chapter 2.
L. Harrison,B. Landell +1 more
TL;DR: In this paper, an overview of complex integrated circuit technology, focusing particularly upon application specific integrated circuits, is presented. But the focus of this paper is on the use of these integrated circuits in fly-by-wire applications.
References
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Journal ArticleDOI
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Journal ArticleDOI
On the Acceleration of Test Generation Algorithms
TL;DR: The FAN (fan-out-oriented test generation algorithm) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel and an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation.
Journal ArticleDOI
Design for testability—A survey
T.W. Williams,Kenneth P. Parker +1 more
TL;DR: A short review of the basics of testability is given in this paper along with some reasons why one should test and different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Journal ArticleDOI
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as discussed by the authors, and the testability is also related to how well the internal nodes can be controlled and observed.