Proceedings ArticleDOI
Design of low-power on-line reconfigurable datapaths using self-checking circuits
Athanasios Kakarountas,Vasileios Kokkinos,Constantinos E. Goutis +2 more
- Vol. 3, pp 1565-1568
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TLDR
A novel technique is illustrated to implement fault-tolerant circuits using on-line testing and a reconfiguration technique to by-pass the erroneous unit and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved.Abstract:
In this paper, a novel technique is illustrated to implement fault-tolerant circuits. On-line testing is used to detect errors and a reconfiguration technique is applied to by-pass the erroneous unit. The main characteristics of this technique are the reduced power dissipation compared to formal implementations and the minimum required time to perform the reconfiguration process. Application of this technique on FIRs is illustrated and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved.read more
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A noncontact charger using a resonant converter with parallel capacitor of the secondary coil
TL;DR: In this article, a noncontact charging system using a resonant converter is presented, where the power transfer ability of a detachable transformer is improved by using a parallel capacitor connected to the secondary coil.
Journal ArticleDOI
Design and synthesis of self-checking VLSI circuits
Niraj K. Jha,Sying-Jyan Wang +1 more
TL;DR: Methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers are examined and the area overhead for all proposed design alternatives is studied in detail.
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A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
A. Tanabe,Toshio Takeshima,Hiroki Koike,Yoshiharu Aimoto,M. Takada,T. Ishijima,Naoki Kasai,Hiromitsu Hada,K. Shibahara,T. Kunio,Takaho Tanigawa,Takanori Saeki,Masato Sakao,Hidenobu Miyamoto,H. Nozue,S. Ohya,T. Murotani,K. Koyama,T. Okuda +18 more
TL;DR: In this article, a 64 Mw*1 b/16 mw*4 b DRAM with 30-ns access time was reported, which uses a double-metal layer and 0.4-mu m CMOS technology.
Journal ArticleDOI
Linear Regulator Design for a Load and Frequency Control
TL;DR: In this article, the results of a dynamic optimization procedure in the design of load and frequency control (LFC) of power systems are presented, based on the optimal linear regulator theory, accommodated to satisfy the performance objectives of the LFC in large multi-area interconnections.
Journal ArticleDOI
A review of fault-tolerant techniques for the enhancement of integrated circuit yield
TL;DR: In this article, the authors examine the ways in which the yield of integrated circuit production can be improved through the use of circuit design techniques, focusing on fault-tolerant approaches but aspects of circuit layout are also briefly considered.