Design of Low Power SRAM Cell Using Adiabatic Logic
Ramya sri Penugonda,V. Ravi +1 more
- Vol. 1716, Iss: 1, pp 012039
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The article was published on 2020-12-01 and is currently open access. It has received 3 citations till now.read more
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Posted ContentDOI
Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder
TL;DR: The aim of this paper is to carry out work that is focused on reducing the power dissipation in circuits, which increases with down scaling of circuits.
Proceedings ArticleDOI
A Novel Low Power Single Bit SRAM Cell Using Quasi-Adiabatic Logic
TL;DR: In this article , a quasi-adiabatic logic is used to slow down the charging and discharging process to reduce the energy dissipation and power consumption of SRAM cells, which is more effective for ultra low power applications where low power consumption is more prioritized than speed.
Proceedings ArticleDOI
A Novel Low Power Single Bit SRAM Cell Using Quasi-Adiabatic Logic
TL;DR: In this paper , a quasi-adiabatic logic is used to slow down the charging and discharging process to reduce the energy dissipation and power consumption of SRAM cells, which is more effective for ultra low power applications where low power consumption is more prioritized than speed.
References
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Journal ArticleDOI
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies
M. H. Ansari,Hassan Afzali-Kusha,Behzad Ebrahimi,Zainalabedin Navabi,Ali Afzali-Kusha,Massoud Pedram +5 more
TL;DR: The proposed 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed and may be considered as one of the better design choices for both high performance and low power applications.
Journal ArticleDOI
Two-phase sinusoidal power-clocked quasi-adiabatic logic circuits
TL;DR: The design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N-2N2p, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources demonstrate the efficiency of sinusoid power clock at both the high and the low frequency ranges of operation.
Proceedings ArticleDOI
Low Standby Power and Robust FinFET Based SRAM Design
TL;DR: The results show considerable improvements in terms of the standby power as well as the hold and read SNM, suggesting that the Vt-control method may be used for realizing low-standby power and robust SRAM.
Journal ArticleDOI
Design and Development of BIST Architecture for Characterization of S-RAM Stability
M. Krishna Chaitanya,V. Ravi +1 more
TL;DR: By using a detection technique which is digitally programmable to detect the defective SRAM cells, cells can be tested even after the fabrication and accordingly one can find out the bit line voltages at which even weak and bad Cells can be made useful.
Book ChapterDOI
Variation-Tolerant In-Memory Digital Computations Using SRAM
TL;DR: In this article, a variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode.