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Experimental Evaluation of Testability Measures for Test Generation
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TLDR
In this article, the authors present results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms, using over 60 000 faults in circuits of varying size and complexity.Abstract:
This paper presents results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms. Each measure was evaluated using over 60 000 faults in circuits of varying size and complexity. The per- formance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The re- sults indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable.read more
Citations
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Journal ArticleDOI
Combinational test generation using satisfiability
TL;DR: The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point.
Journal ArticleDOI
New Techniques for Deterministic Test Pattern Generation
Ilker Hamzaoglu,Janak H. Patel +1 more
TL;DR: New techniques for speeding up deterministic test pattern generation for VLSI circuits by reducing number of backtracks with a low computational cost are presented and incorporated into an advanced ATPG system for combinational circuits called ATOM.
Journal ArticleDOI
A parallel branch and bound algorithm for test generation
S. Patil,Prithviraj Banerjee +1 more
TL;DR: It is shown that parallel processing of HTD faults does indeed result in high fault coverage, which is otherwise not achievable by a uniprocessor algorithm, and the parallel algorithm exhibits superlinear speedups in some cases due to search anomalies.
Proceedings ArticleDOI
New techniques for deterministic test pattern generation
Ilker Hamzaoglu,Janak H. Patel +1 more
TL;DR: New techniques for speeding up deterministic test pattern generation for VLSI circuits by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation are presented.
Proceedings ArticleDOI
Fault partitioning issues in an integrated parallel test generation/fault simulation environment
S. Patil,Prithviraj Banerjee +1 more
TL;DR: The authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle and present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits.
References
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Journal ArticleDOI
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Journal ArticleDOI
On the Acceleration of Test Generation Algorithms
TL;DR: The FAN (fan-out-oriented test generation algorithm) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel and an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation.
Proceedings Article
Socrates : A Highly Efficient Automatic Test Pattern Generation System
TL;DR: SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Journal ArticleDOI
SOCRATES: a highly efficient automatic test pattern generation system
TL;DR: SOCRATES as discussed by the authors is an automatic test pattern generation system for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.