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Journal ArticleDOI

Exploiting Resonant Behavior to Reduce Inductive Noise

Michael D. Powell, +1 more
- Vol. 32, Iss: 2, pp 288-299
TLDR
This proposal changes the frequency of current variations away from the resonance band to a non-resonant frequency to be absorbed by the power supply, because inductive noise is a resonance problem.
Abstract
Inductive noise in high-performance microprocessors is a reliabilityissue caused by variations in processor current (di/dt)which are converted to supply-voltage glitches by impedances inthe power-supply network. Inductive noise has been addressed byusing decoupling capacitors to maintain low impedance in thepower supply over a wide range of frequencies. However, evenwell-designed power supplies exhibit (a few) peaks of high impedanceat resonant frequencies caused by RLC resonant loops. Previousarchitectural proposals adjust current variations bycontrolling instruction fetch and issue, trading off performanceand energy for noise reduction. However, the proposals do notconsider some conceptual issues and have implementation challenges.The issues include requiring fast response, responding tovariations that do not threaten the noise margins, or respondingto variations only at the resonant frequency while the range ofhigh impedance extends to a resonance band around the resonantfrequency. While previous schemes reduce the magnitude of variations,our proposal, called resonance tuning, changes the frequencyof current variations away from the resonance band to anon-resonant frequency to be absorbed by the power supply.Because inductive noise is a resonance problem, resonance tuningreacts only to repeated variations in the resonance band, andnot to isolated variations. Reacting after a few repetitions allowsmore time for the response and reduces unnecessary responses,decreasing performance and energy loss.

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Citations
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References
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Journal ArticleDOI

The SimpleScalar tool set, version 2.0

TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.
Proceedings ArticleDOI

Wattch: a framework for architectural-level power analysis and optimizations

TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Book

Elementary Differential Equations and Boundary Value Problems

TL;DR: In this article, elementary differential equations and boundary value problems are studied in the context of boundary value problem, where boundary value is defined as a function of the boundary value of the elementary differential equation.
Book

Digital Integrated Circuits

TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Book

Digital Integrated Circuits

TL;DR: The properties and definitions of Digital ICS are summarized in the partial table of contents.
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