Journal ArticleDOI
Fast radix-2 division with quotient-digit prediction
Milos D. Ercegovac,Tomás Lang +1 more
- Vol. 1, Iss: 3, pp 169-180
TLDR
An implementation of a radix-2 division unit that uses prediction of the quotient digit to achieve a simple quotient-digit selection, resulting in a step time roughly half of that of SRT division (without prediction).Abstract:
An implementation of a radix-2 division unit is presented that uses prediction of the quotient digit. This prediction allows the concurrent computation of the quotient digit and the partial remainder. To achieve a simple quotient-digit selection, resulting in a step time roughly half of that of SRT division (without prediction), a simple estimate of the partial remainder is used, which requires that the divisor be scaled close to unity. This prescaling is simple to implement and increases the execution time by two cycles. We estimate a speed-up of 1.5 with respect to SRT division with redundant remainders.read more
Citations
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Journal ArticleDOI
Fast division using accurate quotient approximations to reduce the number of iterations
D.C. Wong,Michael J. Flynn +1 more
TL;DR: A class of iterative integer division algorithms is presented based on look-up table and Taylor-series approximations to the reciprocal, which naturally produce an exact remainder, which is very useful for implementing precise rounding specifications.
Proceedings ArticleDOI
New algorithms and VLSI architectures for SRT division and square root
TL;DR: Radix two algorithms for SRT division and square-rooting are developed, where the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped.
Proceedings ArticleDOI
High-speed VLSI arithmetic processor architectures using hybrid number representation
H.R. Srinivas,Keshab K. Parhi +1 more
TL;DR: This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations, and presents a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and uses this to design a bit-Parallel multiplier.
Journal ArticleDOI
Over-redundant digit sets and the design of digit-by-digit division units
Paolo Montuschi,Luigi Ciminiera +1 more
TL;DR: New techniques for the direct computation of division, that use an over-redundant digit set for representing the quotient, instead of simply redundant ones used previously, are presented.
Journal ArticleDOI
High-speed VLSI arithmetic processor architectures using hybrid number representation
H.R. Srinivas,Keshab K. Parhi +1 more
TL;DR: In this article, the authors propose newshifted remainder conditioning, and sign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures.
References
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Journal ArticleDOI
A New Class of Digital Division Methods
TL;DR: A class of division methods best suited for use in digital computers with facilities for floating point arithmetic by considering the nature of each quotient digit as generated during the division process is described.
Journal ArticleDOI
On-the-Fly Conversion of Redundant into Conventional Representations
Ercegovac,Lang +1 more
TL;DR: An algorithm to convert redundant number representations into conventional representations is presented, which is applicable in arithmetic algorithms such as nonrestoring division, square root, and on-line operations in which redundantly represented results are generated in a digit-by-digit manner.
Journal ArticleDOI
Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
TL;DR: The nature of a class of division techniques which permit the selection of quotient digits in digital division by the inspection of truncated versions of the divisor and partial remainder is reviewed in detail.
Proceedings ArticleDOI
Design of high speed MOS multiplier and divider using redundant binary representation
TL;DR: This work improved the algorithm and the method of implementation, and designed an advanced multiplier and divider for MOS LSI based on a new algorithm that has several excellent features such as high speed addition operations.