Flexible phase-locked loops and millimeter wave PLL components for 60-GHz wireless networks in CMOS

TLDR: In this work, frequency synthesizers as enabling sub-systems for 60 GHz transceivers have been presented and a systematic top-down approach was adopted which included the system analysis followed by design and implementation of critical synthesizer components and finally their combined integration to form the proposed synthesizer.

Abstract: The 60 GHz license-free frequency band offers the possibility of multi-gigabit per second wireless transmission satisfying the increasing demand of data intensive applications over short distances. Over the last decade, aggressive down-scaling of CMOS technologies coupled with an intensive research effort has made the realization of complete 60 GHz systems, a reality. In this work, frequency synthesizers as enabling sub-systems for 60 GHz transceivers have been presented. In order to accomplish an accurately functioning overall system, a systematic top-down approach was adopted which included the system analysis followed by design and implementation of critical synthesizer components and finally their combined integration to form the proposed synthesizer. Experience of the complete design flow at mm-wave frequencies was attained that, apart from circuit design solutions, included specialized layout and measurement techniques. Chapter 2 laid down the system architecture of the synthesizer. The channelization specifications for the synthesizer were extracted from the IEEE 802.15.3c which is a standard still in works. The proposed channels were either based on 2 GHz HRP for data intensive applications or 1 GHz and 500 MHz LRP channels for moderate and low data rate applications, respectively. A flexible synthesizer architecture was proposed with the aim to support a number of potential frequency conversion techniques which can be adopted for a 60 GHz transceiver. While re-using the same back-end and by adopting flexible synthesizer front-ends, the proposed architecture supported the sliding-IF topology and the direct conversion topology with and without a frequency tripler. An overview of synthesizer basics was also included followed by calculations and system level simulations of the overall system. In chapter 3, the impact of layout parasitics and sensitivity of measurements at mm-wave frequencies and the techniques employed in this work to address them were elaborated. For mm-wave layout there are no-rules but only guidelines. Distributed analysis at mm-wave frequencies is not only required due to small wavelengths but also because the interconnect parasitics become of the same order as the passive structures. Therefore, a maximum tolerable interconnect length based on the operation frequency and the circuit application needs to be determined. Furthermore, the circuit floor-planning becomes important and should be done in a way to minimize interconnect lengths. In addition to the usual RC-extraction, EM-solvers need to be utilized for critical interconnects for inductance extraction. In order to reduce substrate losses, cross-talk and coupling between components, shielding techniques such as meshed grounding, coplanar transmission lines, and guard-rings should be utilized. The second half of chapter 3 was dedicated to mm-wave IC measurement issues such as losses, mismatches and variation in the equipment, cables, connectors, probe position and temperature. In general, the measurement plane has to be shifted close to the DUT by performing accurate and regular calibrations. Furthermore, the measurement environment should be kept quiet to avoid external noise corrupting the on-chip signals. To obtain stable and repeatable results, physical change in the setups must be avoided and a considerable number of samples should be measured to average out the unwanted contributions in the measured results. Chapter 4 focused on the synthesizer front-end components which operate at the highest frequencies in the synthesizer and are the most challenging blocks. A step wise approach was adopted, starting with individual component design of the prescalers and VCOs and concluding with an integrated front-end. An overview of different prescaler architectures revealed that static and dynamic frequency dividers are easy to design and provide wide locking range; however, they fall short of reaching close to 60 GHz. Injection locked frequency dividers, on the other hand, are able to operate at mm-wave frequencies but their narrow-band nature results in smaller locking range. Thus, circuit design techniques have been adopted to improve the latter characteristic. Three examples of injection locked frequency dividers were presented. The 40 GHz divide-by-2 quadrature ILFD based on direct injection used an input power matching technique by utilizing interconnect inductance to cancel-out parasitic capacitance of the injection transistor. This enhanced the injection efficiency and resulted in a wide locking range. The 60 GHz divide-by-3 ILFD on the other hand addressed the locking range issue by adopting harmonic enhancement through resistive feedback. The last prescaler presented for the proposed synthesizer combined the divide-by-2 and divide-by-3 operations in one circuit, thus simplifying the overall system architecture considerably. New figure-of-merits were introduced for frequency dividers for a proper comparison especially between ILFDs with or without varactor tuning. The introduced FOMs also incorporated the DC power consumption and input sensitivity, which are important performance benchmarks for ILFDs. The second major section of chapter 4 was dedicated to the voltage controlled oscillator. An overview of various VCO architectures was presented among which LC based VCOs were found to be suitable for 60 GHz frequency operation with reasonable tuning range and phase noise. Three LC-VCO circuits were presented next. The VCO for the 40 GHz front-end was a complementary cross-coupled structure and employed differential tuning for the capacitive tuning circuit. Two I-Q VCOs for the 60 GHz synthesizer front-end were presented next. The first was based on active coupling using transistors whereas the second was based on passive coupling using on-chip transformers. The transformer was measured as a separate test-structure and provided reasonable between EM simulations and measurements. By way of analysis, it was found that a dual-band VCO (operating at 40 and 60 GHz) utilizing switches and with satisfactory FTR was very difficult to achieve. This was because either the losses of the switch were too high, which degraded the tank Q-factor, or the fixed capacitance added to the tank was too large, which decreased the tuning range. Therefore, two separate VCOs operating at the aforementioned frequencies were adopted as a way-forward for synthesizer front-end integration. The last section of chapter 4 presented the integrated synthesizer front-ends at 40 and 60 GHz which was an important step towards complete system integration. The main challenge in combining the two front-end components was to align their operating ranges. In chapter 5, the synthesizer back-end components including the low frequency dividers, phase frequency detector, charge pump and loop filter were presented. Although working at lower frequencies, these components entailed challenges such as accuracy, matching and robustness. Two approaches for feedback division namely cascaded divide-by-2 stages and mixer based division were demonstrated. The former was optimized for low power consumption by reducing the transistor dimensions and moderately increasing the load resistors. The mixer based approach offered further reduction of power consumption; however, it required a fixed and accurate LO for down-converting the ILFD output to a frequency close to the reference frequency of the synthesizer. The PFD, based on D-flip-flops, was constructed by custom made NAND gates and the dead-zone was eliminated by inserting intentional delay in the reset path. The charge-pump was optimized for matching between up and down currents and voltage drops across transistors were equalized by using dummy transistors. The second order loop filter was combined with the PFD and charge-pump to determine the response of the back-end to increasing or decreasing phase and frequency difference. Finally in chapter 6, building on the components and sub-circuit designs of preceding chapters, complete synthesizers based on our proposed flexible architecture were presented. Using the expertise from chapter 4 of VCO, ILFD and front-end design, the integration of the complete 40 GHz synthesizer was considerably simplified and the measured and simulated results matched very closely. Based on the 40 GHz components, a single-mode synthesizer for 60 GHz sliding-IF system was presented first. It demonstrated sufficient locking range to cover the 60 GHz frequency band from 57 to 65 GHz. Furthermore, the measured phase noise, settling time and power consumption were comparable to the state-of-the-art published synthesizers. The next synthesizer replaced the divider chain in the feedback loop with a mixer operated by an external LO signal. For testing purposes, the reference frequency was fixed and the output of the synthesizer was set by varying the mixer LO frequency. At simulation level, this setup offered savings in silicon area and power consumption. However, it had a drawback of an extra LO frequency. Finally, a dual-mode synthesizer matching the proposed architecture was presented which included the 40 and 60 GHz VCOs, both connected to a single dual-mode ILFD. In the 60 GHz direct-conversion mode, the tuning-range of the VCO was found to be a limiting factor and the presented design could only cover eleven out of twelve 500 MHz LRP channels. Combining the performance parameters of the two individual synthesizers, the dual-mode synthesizer provides an elegant solution for sliding-IF as well as direct-conversion transceivers with or without using a frequency tripler.