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Patent

Flip-flop circuit with short propagation delay

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TLDR
In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected as mentioned in this paper, and latch switches are inserted between the inverters and the corresponding data inputs terminals.
Abstract
In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected. Latch switches are inserted between the inverters and the corresponding data input terminals. Hold switches are inserted in the cross-connected portion of the two inverters. The latch switches are turned on/off in synchronism with a latch input while the hold switches are turned on/off in synchronism with a hold input.

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Patent

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Kiyoshi Kato, +1 more
TL;DR: In this paper, a nonvolatile latch circuit and a semiconductor device using the latch circuit was proposed, which includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element; and a data holding portion for holding data of the latch portion.
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References
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Patent

High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates

TL;DR: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters as discussed by the authors, which allows data to enter the latch when the latch is disabled.
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LSSD Compatible clock driver

TL;DR: In this paper, a latch-type clock driver circuit for level sensitive scan design (LSSD) testing is presented, which enables the carrying out of LSSD testing.
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Dynamically selectable polarity latch

TL;DR: In this paper, a selective true or complement storage latch is disclosed which includes a data input switch having an input node connecting to a binary bit input source, a control input for accepting a first or second control state, a first data output node which is selectively connected to the data input node when the control input is in the first state and a second data output nodes which are selectively connected with the data inputs when the controller input was in the second state.
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Electronic counter for electrical digital pulses

TL;DR: In this article, an electronic counter is provided for electrical digital pulses including a counter chain comprising idential flip-flop cells to be controlled by way of a counting input by means of pulses to be counted.