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Open AccessJournal ArticleDOI

FPGA Programming for the Masses: The programmability of FPGAs must improve if they are to be part of mainstream computing.

David F. Bacon, +2 more
- 22 Feb 2013 - 
- Vol. 11, Iss: 2, pp 40-52
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TLDR
When looking at how hardware influences computing performance, the authors have GPPs (general-purpose processors) on one end of the spectrum and ASICs (application-specific integrated circuits) on the other.
Abstract
When looking at how hardware influences computing performance, we have GPPs (general-purpose processors) on one end of the spectrum and ASICs (application-specific integrated circuits) on the other. Processors are highly programmable but often inefficient in terms of power and performance. ASICs implement a dedicated and fixed function and provide the best power and performance characteristics, but any functional change requires a complete (and extremely expensive) re-spinning of the circuits.

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Citations
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Plasticine: A Reconfigurable Architecture For Parallel Paterns

TL;DR: This work designs Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns that provide an improvement of up to 76.9× in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.
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Literature Survey on Stereo Vision Disparity Map Algorithms

TL;DR: This literature survey presents a method of qualitative measurement that is widely used by researchers in the area of stereo vision disparity mappings and notes the implementation of previous software-based and hardware-based algorithms.
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Spatial: a language and compiler for application accelerators

TL;DR: This work describes a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators, and summarizes the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning.
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Deep Learning for Mobile Multimedia: A Survey

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Automatic generation of efficient accelerators for reconfigurable hardware

TL;DR: A hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing is described.
References
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Hitting the memory wall: implications of the obvious

TL;DR: This work proposes an exact analysis, removing all remaining uncertainty, based on model checking, using abstract-interpretation results to prune down the model for scalability, and notably improves precision upon classical abstract interpretation at reasonable cost.
Proceedings ArticleDOI

Chisel: constructing hardware in a Scala embedded language

TL;DR: Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages, is introduced by embedding Chisel in the Scala programming language, raising the level of hardware design abstraction.
Book

High-Level Synthesis: from Algorithm to Digital Circuit

TL;DR: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia, and should be on each designers and CAD developers shelf.
Proceedings ArticleDOI

From opencl to high-performance hardware on FPGAS

TL;DR: It is shown that the OpenCL computing paradigm is a viable design entry method for high-performance computing applications on FPGAs and that it can achieve a clock frequency in excess of 160MHz on benchmarks.
Journal ArticleDOI

State-of-the-art in heterogeneous computing

TL;DR: In this paper, the authors present an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs).