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Proceedings ArticleDOI

GPU Versus FPGA for High Productivity Computing

TLDR
It is shown that the GPU is more productive than the FPGA architecture for most of the benchmarks and it is concluded thatFPGA-based HPCS is being marginalised by GPUs.
Abstract
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is compared with the performance of a commercially available FPGA based HPC. Contrary to previous approaches that focussed on specific examples, a broader analysis is performed by considering processes at an architectural level. A set of benchmarks is employed that use different process architectures in order to exploit the benefits of each technology. These include the asynchronous pipelines common to "map" tasks, a partially synchronous tree common to "reduce" tasks and a fully synchronous, fully connected mesh. We show that the GPU is more productive than the FPGA architecture for most of the benchmarks and conclude that FPGA-based HPCS is being marginalised by GPUs.

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Proceedings ArticleDOI

Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing

TL;DR: Evaluating the High-Productivity Reconfigurable Computer (HPRC) approach to FPGA programming, where a commodity CPU instruction set architecture is augmented with instructions which execute on a specialised FPGa co-processor, shows that high-productivity reconfigurable computing systems outperform GPUs in applications with poor locality characteristics and low memory bandwidth requirements.
Journal ArticleDOI

The Chimera: an off-the-shelf CPU/GPGPU/FPGA hybrid computing platform

TL;DR: A heterogeneous CPU/GPGPU/FPGA desktop computing system built with commercial-off-the-shelf components is described, showing that this platform may be a viable alternative solution to many common computationally bound problems found in astronomy, however, not without significant challenges.
Proceedings ArticleDOI

VirtualRC: a virtual FPGA platform for applications and tools portability

TL;DR: This paper addresses the portability challenge by introducing a framework of architecture and middleware for virtualization of FPGA platforms, collectively named VirtualRC, and enabling portability of 11 applications and two high-level synthesis tools across three physical platforms.
Journal ArticleDOI

Server Selection, Configuration and Reconfiguration Technology for IaaS Cloud with Multiple Server Types

TL;DR: A server selection, configuration, reconfiguration and automatic performance verification technology to meet user functional and performance requirements on various types of cloud compute servers to enable cloud providers to provision compute resources on appropriate hardware based on user requirements.
Journal ArticleDOI

Performance Characterization and Design Guidelines for Efficient Processor–FPGA Communication in Cyclone V FPSoCs

TL;DR: This paper presents an extensive characterization and analysis of processor-FPGA communications in a widely used family of FPSoCs, namely Cyclone V devices, and introduces a set of design guidelines to help FPSoC designers take the most possible advantage of the excellent characteristics of these devices.
References
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Journal ArticleDOI

Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator

TL;DR: A new algorithm called Mersenne Twister (MT) is proposed for generating uniform pseudorandom numbers, which provides a super astronomical period of 2 and 623-dimensional equidistribution up to 32-bit accuracy, while using a working area of only 624 words.
Proceedings ArticleDOI

Axel: a heterogeneous cluster with FPGAs and GPUs

TL;DR: A Map-Reduce framework for the Axel cluster is presented which exploits spatial and temporal locality through different types of processing elements and communication channels, and enables the first demonstration of FPGAs, GPUs and CPUs running collaboratively for N-body simulation.
Journal ArticleDOI

Instruction Set Innovations for the Convey HC-1 Computer

Tony M Brewer
- 01 Mar 2010 - 
TL;DR: The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system.

Overview of Recent Supercomputers

TL;DR: The main architectural classes, as well as general computational accelerators, are summarized.
Journal ArticleDOI

Examining the viability of FPGA supercomputing

TL;DR: A comparative analysis of FPGAs and traditional processors is presented, focusing on floating-point performance and procurement costs, revealing economic hurdles in the adoption of FFPAs for general high-performance computing (HPC).
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We show that the GPU is more productive than the FPGA architecture for most of the benchmarks and conclude that FPGA-based HPCS is being marginalised by GPUs.