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Handbook of Algorithms for Physical Design Automation

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Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
Abstract
The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology. Includes a personal perspective from Ralph Otten as he looks back on the major technical milestones in the history of physical design automation. Explore State-of-the-Art Techniques and TrendsHandbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. Highly-Focused Information for Next Generation Design Problems Although several books on this topic are currently available, most are either too broad or out of date. Alternatively, proceedings and journal articles are valuable resources for researchers in this area, but the material is widely dispersed in the literature. This handbook pulls together a broad variety of perspectives on the most challenging problems in the field, and focuses on emerging problems and research results.

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Book ChapterDOI

ASIC Implementation of AI Edge Network on Chip (NoC) at 28 nm Technology Node and Its Various Timing Optimization Techniques at Each Stage

Afrasyab Khan
TL;DR: In this paper , the authors discuss the physical design of a network on chip (NoC) with various optimization techniques used at each stage, which is intended to reduce worst negative slack (WNS).
Proceedings ArticleDOI

Intelligent Decision-Making Based on Self-Organization

TL;DR: The article has concerned a statement of the parametric optimization problem, which involves bioinspired self-organization algorithms based on the behaviour of bats and monkeys in nature and a model of the optimization problem based on bats behaviour.
Proceedings ArticleDOI

Combined approach for VLSI placement problem

TL;DR: A new search architecture based on the proposed "evolution" "search" strategy is constructed and a combined algorithm has been developed that allows to improve the result found by the genetic algorithm.
Proceedings ArticleDOI

BufFormer: A Generative ML Framework for Scalable Buffering

TL;DR: In this article , a generative ML framework, BufFormer, is proposed to construct abstract tree topology while simultaneously determining buffer sizes and locations, which can extract and reuse knowledge from high quality samples and therefore has significantly improved scalability.
Book ChapterDOI

The Algorithm of the Unified Mechanism for Encoding and Decoding Solutions When Placing VLSI Components in Conditions of Different Orientation of Different-Sized Components

TL;DR: In this paper , a modified GA with a mechanism for encoding and decoding of solutions in bio-inspired automated design was proposed for the placement of VLSI components on a crystal, where the modification consists in the application of a new encoding-and decoding mechanism in the conditions of different orientation of different-sized components.
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