Book ChapterDOI
HIBI v.2 Communication Network for System-on-Chip
Erno Salminen,Vesa Lahtinen,Tero Kangas,Jouni Riihimäki,Kimmo Kuusilinna,Timo Hämäläinen +5 more
- pp 413-422
TLDR
The Heterogeneous IP Block Interconnection v.2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers.Abstract:
This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs The Heterogeneous IP Block Interconnection v2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers Other features include support for arbitrary topologies with several clock domains, flexible scalablility in signalling and run-time reconfiguration of network parameters HIBI has been implemented in VHDL and SystemC and synthesized in 018 CMOS technology with area comparable to other NoC wrappers HIBI data transfers are shown to approach the maximum theoretical performance for protocol efficiencyread more
Citations
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Journal ArticleDOI
UML-based multiprocessor SoC design framework
Tero Kangas,Petri Kukkala,Heikki Orsila,Erno Salminen,Marko Hännikäinen,Timo Hämäläinen,Jouni Riihimäki,Kimmo Kuusilinna +7 more
TL;DR: The design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC.
Journal Article
Networks on Chips
TL;DR: This paper is meant to be a short introduction to a network on chip(NOC) design methodology that extends the platform based design approaches to the systems with on-chip networks and heterogeneous computing resources.
Proceedings ArticleDOI
A parallel MPEG-4 encoder for FPGA based multiprocessor SoC
TL;DR: The main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA and the interconnections between memories and processors are realized with the HIBI network.
Patent
Software implementation of matrix inversion in a wireless communication system
TL;DR: In this article, a vector unit, first and second registers coupled to and accessible by the vector unit and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions is presented.
Proceedings ArticleDOI
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications
TL;DR: This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0, and is the first real implementation combining a high-level design flow with a synthesizable platform.
References
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Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
A generic architecture for on-chip packet-switched interconnections
Pierre Guerrier,Alain Greiner +1 more
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
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Journal ArticleDOI
QNoC: QoS architecture and design process for network on chip
TL;DR: A customized Quality-of-Service NoC (QNoC) architecture is derived by modifying a generic network architecture which minimizes the network cost while maintaining the required QoS.
Book ChapterDOI
Networks on chip
Axel Jantsch,Hannu Tenhunen +1 more
TL;DR: There is a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems.