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Proceedings ArticleDOI

Design and implementation of real time secured RS232 link for multiple FPGA communication

12 Feb 2011-pp 391-396

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Citations
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Journal ArticleDOI
TL;DR: This is Applied Cryptography Protocols Algorithms And Source Code In C Applied Cryptographic Protocols algorithms and Source Code in C By Schneier Bruce Author Nov 01 1995 the best ebook that you can get right now online.
Abstract: ebooks and guide Applied Cryptography Protocols Algorithms And Source Code In C Applied Cryptography Protocols Algorithms And Source Code In C By Schneier Bruce Author Nov 01 1995. This is Applied Cryptography Protocols Algorithms And Source Code In C Applied Cryptography Protocols Algorithms And Source Code In C By Schneier Bruce Author Nov 01 1995 the best ebook that you can get right now online.

135 citations

Proceedings ArticleDOI
15 Mar 2012
TL;DR: This research work proposes the design and implementation of a real-time FPGA based application, which demonstrates the creation ofreal-time process tasks in FGPA systems for successful real- time communication between multiple FPGAs.
Abstract: The recent development of Field-Programmable Gate Array (FPGA) architectures, with soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and IP cores, offers the potential for high computing power. Presently FPGAs are considered as a major platform for high performance embedded applications as it provides the opportunity for reconfiguration as well as good clock speed and design resources. As the complexities in the embedded applications increase, use of an operating system brings in a lot of advantages. In present day application scenarios most embedded systems have real-time requirements that demand the use of Real-time operating systems (RTOS), which creates a suitable environment for real time applications to be designed and expanded easily. In an RTOS the design process is simplified by splitting the application code into separate tasks and then the scheduler executes them according to a specific schedule, meeting the real-time deadline. In this research work, we propose the design and implementation of a real-time FPGA based application, which demonstrates the creation of real-time process tasks in FPGA systems for successful real-time communication between multiple FPGA systems. We have chosen the RSA based encryption and decryption algorithm for this implementation, as security is one of the most important need for data communication. At first we demonstrate the real-time execution of multiple process tasks in a single FPGA system for the encryption and decryption of data. Next we describe the most challenging part of our work, where we establish the real-time communication between two FPGA systems, each running the encryption engine and decryption engine respectively and communicating with one another via an RS232 communication link. The results show that our design is better in terms of execution speed in comparison with the existing research works.

6 citations

Proceedings ArticleDOI
03 Aug 2012
TL;DR: Hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers is needed in terms of larger key values, higher throughput and less resource utilization.
Abstract: Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.

5 citations

Journal ArticleDOI
23 Dec 2015
TL;DR: The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI and the implementation of read out chain of Muon Cliamber(MUCH) in India is tried to implement FPGA based emulator of GBTx in India.
Abstract: The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected through optical fiber through small form-factor pluggable (SFP) port. We have tested the setup in the runtime environment using Xilinx Cliipscope Pro Analyzer. We also measure the resource utilization, throughput., power optimization of implemented design.

1 citations

Journal Article
TL;DR: This project uses Xilinx ISE 14.7i that is associate microcircuit development platform supported the Xilxin ISE 13.3i tool and tends to customize the planning of AES formula to implement merely onXilinx software package to facilitate the developers to change and use the software package simply with none issues throughout installation of style.
Abstract: With the present omnipresence of pc networks, distributed systems generally, and also the net particularly, cryptography has become associate enabling technology to secure the data, infrastructures we tend to area unit building, using, and hoping on in way of life. In gift days, nearly each relevant communication system needs secure information transfer so as to keep up the privacy of the transmitted message. Hardware implementation on FPGA offers a faster and customizable answer. we tend to use Verilog Language for synthesizing logic style. This project uses Xilinx ISE 14.7i that is associate microcircuit development platform supported the Xilinx ISE 14.7i tool. Software package implementation on Xilinx is often advanced style and in counter mode it becomes the foremost complex drawback. we tend to customize the planning of AES formula to implement merely on Xilinx software package. This may later facilitate the developers to change and use the software package simply with none issues throughout installation of style. Some key blessings of AES encryption and coding formula are unit quick in execution and it additionally uses higher length sizes 128,192 and 256 bits for encryption which provides additional security to the information because it needs 2 tries to deploy or hack the information.

1 citations


References
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Journal ArticleDOI
TL;DR: An encryption method is presented with the novel property that publicly revealing an encryption key does not thereby reveal the corresponding decryption key.
Abstract: An encryption method is presented with the novel property that publicly revealing an encryption key does not thereby reveal the corresponding decryption key. This has two important consequences: (1) Couriers or other secure means are not needed to transmit keys, since a message can be enciphered using an encryption key publicly revealed by the intented recipient. Only he can decipher the message, since only he knows the corresponding decryption key. (2) A message can be “signed” using a privately held decryption key. Anyone can verify this signature using the corresponding publicly revealed encryption key. Signatures cannot be forged, and a signer cannot later deny the validity of his signature. This has obvious applications in “electronic mail” and “electronic funds transfer” systems. A message is encrypted by representing it as a number M, raising M to a publicly specified power e, and then taking the remainder when the result is divided by the publicly specified product, n, of two large secret primer numbers p and q. Decryption is similar; only a different, secret, power d is used, where e * d ≡ 1(mod (p - 1) * (q - 1)). The security of the system rests in part on the difficulty of factoring the published divisor, n.

14,611 citations

Book
10 Nov 1993
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Abstract: CRYPTOGRAPHIC PROTOCOLS. Protocol Building Blocks. Basic Protocols. Intermediate Protocols. Advanced Protocols. Esoteric Protocols. CRYPTOGRAPHIC TECHNIQUES. Key Length. Key Management. Algorithm Types and Modes. Using Algorithms. CRYPTOGRAPHIC ALGORITHMS. Data Encryption Standard (DES). Other Block Ciphers. Other Stream Ciphers and Real Random-Sequence Generators. Public-Key Algorithms. Special Algorithms for Protocols. THE REAL WORLD. Example Implementations. Politics. SOURCE CODE.source Code. References.

3,414 citations

Book ChapterDOI
12 Aug 1999
TL;DR: The general view of the new architecture is described, hardware organization for its parallel computation is analyzed, and design tradeoffs which are useful to identify the best hardware configuration are discussed.
Abstract: This paper describes the methodology and design of a scalable Montgomery multiplication module. There is no limitation on the maximum number of bits manipulated by the multiplier, and the selection of the word-size is made according to the available area and/or desired performance. We describe the general view of the new architecture, analyze hardware organization for its parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration.

185 citations


"Design and implementation of real t..." refers methods in this paper

  • ...In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA…...

    [...]

  • ...In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface....

    [...]

  • ...2.1 Hardware Architectural Design This work is implemented using the Xilinx EDK 11.4 (version) and Xilinx Spartan 3E FPGA prototyping board has been used for the hardware implementation and testing....

    [...]

  • ...Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, No. 1717, pp. 94-108....

    [...]

  • ...Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, Springer....

    [...]

Book ChapterDOI
14 May 2001
TL;DR: This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work that is proven to be correct and the hardware design is discussed in detail.
Abstract: This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and the hardware design is discussed in detail. Experimental results are shown to compare a radix-8 implementation witha radix-2 design. The scalable Montgomery multiplier is adjustable to constrained areas yet being able to work on any given precision of the operands. Similar to some systolic implementations, this design avoid the high load on signals that broadcast to several components, making the delay independent of operand's precision.

116 citations


"Design and implementation of real t..." refers methods in this paper

  • ...In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA…...

    [...]

  • ...In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface....

    [...]

  • ...2.1 Hardware Architectural Design This work is implemented using the Xilinx EDK 11.4 (version) and Xilinx Spartan 3E FPGA prototyping board has been used for the hardware implementation and testing....

    [...]

  • ...Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, No. 1717, pp. 94-108....

    [...]

  • ...Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, Springer....

    [...]