Proceedings ArticleDOI
Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
Hui Zhang,Marlene Wan,Varghese George,Jan M. Rabaey +3 more
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TLDR
The results indicate that the hierarchical generalized mesh structure shows the most promise in terms of energy efficiency, as it can optimize both local and global connections.Abstract:
In this paper we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect architectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results indicate that the hierarchical generalized mesh structure shows the most promise in terms of energy efficiency, as it can optimize both local and global connections.read more
Citations
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Proceedings ArticleDOI
Orion: a power-performance simulator for interconnection networks
TL;DR: Orion is presented, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power- performance trade-offs at the architectural-level.
Journal ArticleDOI
Power reduction techniques for microprocessor systems
TL;DR: It is concluded that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level and it remains too early to tell which techniques will ultimately solve the power problem.
Proceedings ArticleDOI
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Luca Benini,G. De Micheli +1 more
TL;DR: This work considers energy consumption reduction, under guaranteed quality of service, as a main objective in system design, in systems on chips that can be designed and produced in five to ten years from today.
Proceedings ArticleDOI
aSOC: A Scalable, Single-Chip Communications Architecture
TL;DR: A new single-chip interconnect architecture, adaptive System-On-a-Chip, is described that not only provides scalable data transfer, but also can be easily reconfigured as application-level communication patterns change.
Journal ArticleDOI
A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing
TL;DR: A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors.
References
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William Tsu,Kip Macy,Atul Joshi,Randy Huang,Norman Walker,Tony Tung,Omid Rowhani,Varghese George,John Wawrzynek,André DeHon +9 more
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