Performance-oriented placement and routing for field-programmable gate arrays
Michael J. Alexander,James P. Cohoon,Joseph L. Ganley,Gabriel Robins +3 more
- pp 80-85
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TLDR
A performance-oriented placement and routing tool for field-programmable gate arrays using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing that optimizes source-sink pathlengths, channel width and total wire-length.Abstract:
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.read more
Citations
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Book ChapterDOI
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz,Jonathan Rose +1 more
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Book
Three-Dimensional Integrated Circuit Design
TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Dissertation
Architectures and algorithms for field-programmable gate arrays with embedded memory
TL;DR: This dissertation develops a circuit generator that stochastically generates realistic circuits with memory that can be used as benchmark circuits in architectural studies and considers the architecture of a stand-alone configurable memory that is flexible enough to implement memory configurations with different numbers of memories, memory widths and depths.
Proceedings ArticleDOI
Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT
TL;DR: A new search-based Satisfiability (SAT) formulation that can handle entire FPGAs, routing all nets concurrently, relies on a recently developed SAT engine that uses systematic search with conflict-directed non-chronological backtracking, capable of handling very large SAT instances.
Journal ArticleDOI
A comparative study of two Boolean formulations of FPGA detailed routing constraints
TL;DR: It is demonstrated that the route-based formulation of Boolean SAT-based routing yields an easier-to-evaluate and more scalable routability Boolean function than the track-based method, providing empirical evidence that a smart/efficient Boolean formulation can achieve significant performance improvement in real-world applications.
References
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Journal ArticleDOI
Optimization by Simulated Annealing
TL;DR: There is a deep and useful connection between statistical mechanics and multivariate or combinatorial optimization (finding the minimum of a given function depending on many parameters), and a detailed analogy with annealing in solids provides a framework for optimization of very large and complex systems.
Journal ArticleDOI
Optimization by simulated annealing: an experimental evaluation. Part I, graph partitioning
TL;DR: This paper discusses annealing and its parameterized generic implementation, describes how this generic algorithm was adapted to the graph partitioning problem, and reports how well it compared to standard algorithms like the Kernighan-Lin algorithm.
Journal ArticleDOI
A fast algorithm for Steiner trees
TL;DR: The heuristic algorithm has a worst case time complexity of O(¦S¦¦V¦2) on a random access computer and it guarantees to output a tree that spans S with total distance on its edges no more than 2(1−1/l) times that of the optimal tree.
Book
The Steiner Tree Problem
TL;DR: The Steiner Ratio Conjecture as a Maximin Problem and Effectiveness of Reductions, and Heuristics Using a Given RMST Algorithms, and two Related Results.
Journal ArticleDOI
A Procedure for Placement of Standard-Cell VLSI Circuits
A.E. Dunlop,B.W. Kernighan +1 more
TL;DR: A method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements is described, based on graph partitioning to identify groups of modules that ought to be close to each other.
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