Proceedings ArticleDOI
Low power and low complexity implementation of LPTV interpolation filter
Sriadibhatla Sridevi,Ravindra Dhuli,K. Baboji +2 more
- pp 1-8
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TLDR
An architecture for low power and low complexity implementation of a linear periodically time varying (LPTV) interpolation filter using thread decomposition (TD) technique which decomposes a filter into finite computational threads is presented.Abstract:
This paper presents an architecture for low power and low complexity implementation of a linear periodically time varying (LPTV) interpolation filter using thread decomposition (TD) technique which decomposes a filter into finite computational threads. TD technique enables us to develop the proposed architecture as a generalization to linear time invariant (LTI) filter structure. The area complexity of the proposed architecture is significantly reduced by optimizing the concurrent threads of the conventional design. Reduction of power consumption is achieved in the proposed design by eliminating futile multiplications and reducing the operating frequency of the multipliers. It involves nearly one fourth the number of adders, multipliers and delay elements compared to the conventional design. The proposed structure is implemented on Virtex FPGA 2vp30-7ff896. From the synthesis results, it is found that the proposed design offers 35.7% reduction in power consumption and 20.6% reduction in device utilization over the conventional design.read more
Citations
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Journal ArticleDOI
Systolic array design space exploration of interpolators for multi-rate systems
TL;DR: This study presents the development and comparison of interpolator systolic array designs and implementations and confirms that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than theventional design.
References
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Journal ArticleDOI
Reconfigurable channel filtering and digital down conversion in optimal CSD space for software defined radio
James T. George,Elizabeth Elias +1 more
TL;DR: Frequency response masking (FRM) filter with continuous coefficients is designed and modified harmony search algorithm is used for finding the optimal canonic signed digit representation for the multiplier-less implementation, which reduces the complexity and power consumption.
Journal ArticleDOI
Multirate specifications via alias-component matrices
TL;DR: Alias-component (modulation) matrices permit systematic specification of multirate structures, and are easily incorporated into model-matching design procedures, which are inappropriate for filterbanks that split the spectrum into rationally related bands.
Journal ArticleDOI
Sample rate conversion filter design for multi-standard software radios
Faheem Sheikh,Shahid Masud +1 more
TL;DR: A programmable and computationally efficient SRC filter design scheme with utilization in the digital IF stage of a software radio has been derived.
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC
TL;DR: This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption.
Proceedings ArticleDOI
Optimized FPGA implementation of Multi-Rate FIR filters through Thread Decomposition
TL;DR: TD-MRFIR (Thread Decomposition MRFIR), an alternative representation and implementation technique, to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition.