Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis
Manoj Kumar,Jayaram Bobba,V. Kamakoti +2 more
- Vol. 2, pp 20922
TLDR
This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-ups available on the FPGA.Abstract:
Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-up tables (LUT) available on the FPGA. This in turn leads to a huge reduction in the area of the FPGA, utilized for mapping an application. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, can lead to additional 50% reduction in area utilized when compared with other methodologies reported in the literature.read more
Citations
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DissertationDOI
Optimierung der Verdrahtbarkeit unter Berücksichtigung heterogener Verdrahtungsressourcen hierarchischer FPGA-Architekturen
TL;DR: Theoretische Grundlagen und Stand der Technik, wirtschaftliche Aspekte ..................................................................................
Proceedings ArticleDOI
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
TL;DR: This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field programmable gate arrays (FPGAs).
Proceedings ArticleDOI
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis
TL;DR: This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis and yields better area-reduction than the previous known algorithms.
Proceedings ArticleDOI
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis
TL;DR: This paper presents the SHAPER, which maps the circuits onto HFPAs using reconvergence analysis and yields 18% better area-reduction than the previous known algorithms.
Power implications of implementing logic using field-programmable gate array embedded memory blocks
TL;DR: This thesis develops a power model for FPGAs that contain embedded memories, and applies it to investigate the impact of various embedded memory architectural parameters on power dissipation when using memories to implement logic.
References
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Journal ArticleDOI
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Jason Cong,Yuzheng Ding +1 more
TL;DR: A theoretical breakthrough is presented which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time.
Proceedings ArticleDOI
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
TL;DR: A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented, the major innovation is a method for choosing gate-level decompositions based on bin packing that is up to 28 times faster than a previous exhaustive approach.
Proceedings ArticleDOI
Logic synthesis for programmable gate arrays
Rajeev Murgai,Yoshihito Nishizaki,Narendra Shenoy,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +4 more
TL;DR: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based.
Proceedings ArticleDOI
Technology mapping of lookup table-based FPGAs for performance
TL;DR: A novel technology mapping algorithm that reduces the delay of combinational circuits implemented with lookup-table-based field-programmable gate arrays (FPGAs) by reducing the number of lookup tables on the critical path.
Journal ArticleDOI
DAG-Map: graph-based FPGA technology mapping for delay optimization
TL;DR: A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented and results show that, on average, DAG-Map reduces both network delay and the number of look-up tables.